X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fsoc%2Fexperiment%2Fdcache.py;h=e1f82b77dc337467c1f9eeff306adc2ade4a7120;hb=41d2c31f6f0d184a57f468d5b157d6e8c0a44af1;hp=a95e28422e399b8357a192c199dd15f98adacb77;hpb=a8a808dd3beec2850dddbb86affa57535a6b3821;p=soc.git diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py index a95e2842..e1f82b77 100644 --- a/src/soc/experiment/dcache.py +++ b/src/soc/experiment/dcache.py @@ -26,16 +26,18 @@ from soc.experiment.wb_types import (WB_ADDR_BITS, WB_DATA_BITS, WB_SEL_BITS, WBIOMasterOut, WBIOSlaveOut) from soc.experiment.cache_ram import CacheRam -from soc.experiment.plru import PLRU +#from soc.experiment.plru import PLRU +from nmutil.plru import PLRU # for test from nmigen_soc.wishbone.sram import SRAM from nmigen import Memory from nmigen.cli import rtlil -if True: - from nmigen.back.pysim import Simulator, Delay, Settle -else: - from nmigen.sim.cxxsim import Simulator, Delay, Settle + +# NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell +# Also, check out the cxxsim nmigen branch, and latest yosys from git +from nmutil.sim_tmp_alternative import Simulator + from nmutil.util import wrap @@ -44,7 +46,7 @@ LINE_SIZE = 64 # Line size in bytes NUM_LINES = 16 # Number of lines in a set NUM_WAYS = 4 # Number of ways TLB_SET_SIZE = 64 # L1 DTLB entries per set -TLB_NUM_WAYS = 2 # L1 DTLB number of sets +TLB_NUM_WAYS = 4 # L1 DTLB number of sets TLB_LG_PGSZ = 12 # L1 DTLB log_2(page_size) LOG_LENGTH = 0 # Non-zero to enable log data collection @@ -120,7 +122,7 @@ layout = """\ .. --------| | TAG_BITS (45) """ print (layout) -print ("Dcache TAG %d IDX %d ROW %d ROFF %d LOFF %d RLB %d" % \ +print ("Dcache TAG %d IDX %d ROW_BITS %d ROFF %d LOFF %d RLB %d" % \ (TAG_BITS, INDEX_BITS, ROW_BITS, ROW_OFF_BITS, LINE_OFF_BITS, ROW_LINE_BITS)) print ("index @: %d-%d" % (LINE_OFF_BITS, SET_SIZE_BITS)) @@ -129,6 +131,8 @@ print ("tag @: %d-%d width %d" % (SET_SIZE_BITS, REAL_ADDR_BITS, TAG_WIDTH)) TAG_RAM_WIDTH = TAG_WIDTH * NUM_WAYS +print ("TAG_RAM_WIDTH", TAG_RAM_WIDTH) + def CacheTagArray(): return Array(Signal(TAG_RAM_WIDTH, name="cachetag_%d" % x) \ for x in range(NUM_LINES)) @@ -168,16 +172,20 @@ assert SET_SIZE_BITS <= TLB_LG_PGSZ, "Set indexed by virtual address" def TLBValidBitsArray(): - return Array(Signal(TLB_NUM_WAYS) for x in range(TLB_SET_SIZE)) + return Array(Signal(TLB_NUM_WAYS, name="tlbvalid%d" % x) \ + for x in range(TLB_SET_SIZE)) def TLBTagEAArray(): - return Array(Signal(TLB_EA_TAG_BITS) for x in range (TLB_NUM_WAYS)) + return Array(Signal(TLB_EA_TAG_BITS, name="tlbtagea%d" % x) \ + for x in range (TLB_NUM_WAYS)) def TLBTagsArray(): - return Array(Signal(TLB_TAG_WAY_BITS) for x in range (TLB_SET_SIZE)) + return Array(Signal(TLB_TAG_WAY_BITS, name="tlbtags%d" % x) \ + for x in range (TLB_SET_SIZE)) def TLBPtesArray(): - return Array(Signal(TLB_PTE_WAY_BITS) for x in range(TLB_SET_SIZE)) + return Array(Signal(TLB_PTE_WAY_BITS, name="tlbptes%d" % x) \ + for x in range(TLB_SET_SIZE)) def HitWaySet(): return Array(Signal(WAY_BITS, name="hitway_%d" % x) \ @@ -190,11 +198,13 @@ def CacheRamOut(): # PLRU output interface def PLRUOut(): - return Array(Signal(WAY_BITS) for x in range(NUM_LINES)) + return Array(Signal(WAY_BITS, name="plru_out%d" % x) \ + for x in range(NUM_LINES)) # TLB PLRU output interface def TLBPLRUOut(): - return Array(Signal(TLB_WAY_BITS) for x in range(TLB_SET_SIZE)) + return Array(Signal(TLB_WAY_BITS, name="tlbplru_out%d" % x) \ + for x in range(TLB_SET_SIZE)) # Helper functions to decode incoming requests # @@ -957,7 +967,7 @@ class DCache(Elaboratable): sync += reservation.valid.eq(1) sync += reservation.addr.eq(r0.req.addr[LINE_OFF_BITS:64]) - def writeback_control(self, m, r1, cache_out): + def writeback_control(self, m, r1, cache_out_row): """Return data for loads & completion control logic """ comb = m.d.comb @@ -976,7 +986,7 @@ class DCache(Elaboratable): with m.Else(): comb += data_fwd.eq(r1.forward_data2) - comb += data_out.eq(cache_out[r1.hit_way]) + comb += data_out.eq(cache_out_row) for i in range(8): with m.If(r1.forward_sel[i]): @@ -1042,7 +1052,7 @@ class DCache(Elaboratable): sync += Display("completing MMU load miss, data=%x", m_out.data) - def rams(self, m, r1, early_req_row, cache_out, replace_way): + def rams(self, m, r1, early_req_row, cache_out_row, replace_way): """rams Generate a cache RAM for each way. This handles the normal reads, writes from reloads and the special store-hit update @@ -1066,7 +1076,7 @@ class DCache(Elaboratable): wr_sel_m = Signal(ROW_SIZE) _d_out = Signal(WB_DATA_BITS, name="dout_%d" % i) - way = CacheRam(ROW_BITS, WB_DATA_BITS, True) + way = CacheRam(ROW_BITS, WB_DATA_BITS, ADD_BUF=True) setattr(m.submodules, "cacheram_%d" % i, way) comb += way.rd_en.eq(do_read) @@ -1079,7 +1089,8 @@ class DCache(Elaboratable): # Cache hit reads comb += do_read.eq(1) comb += rd_addr.eq(early_req_row[:ROW_BITS]) - comb += cache_out[i].eq(_d_out) + with m.If(r1.hit_way == i): + comb += cache_out_row.eq(_d_out) # Write mux: # @@ -1572,7 +1583,7 @@ class DCache(Elaboratable): use_forward1_next = Signal() use_forward2_next = Signal() - cache_out = CacheRamOut() + cache_out_row = Signal(WB_DATA_BITS) plru_victim = PLRUOut() replace_way = Signal(WAY_BITS) @@ -1637,8 +1648,8 @@ class DCache(Elaboratable): r0_valid, r0, reservation) self.reservation_reg(m, r0_valid, access_ok, set_rsrv, clear_rsrv, reservation, r0) - self.writeback_control(m, r1, cache_out) - self.rams(m, r1, early_req_row, cache_out, replace_way) + self.writeback_control(m, r1, cache_out_row) + self.rams(m, r1, early_req_row, cache_out_row, replace_way) self.dcache_fast_hit(m, req_op, r0_valid, r0, r1, req_hit_way, req_index, req_tag, access_ok, tlb_hit, tlb_hit_way, tlb_req_index)