X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fsoc%2Fexperiment%2Fsim.py;h=aebb51de404f11d51aa2006f5ee0109f773e972f;hb=7f708f59784c0b424093dd9aa4cfc6cd5e730c7b;hp=1c725b25798a56e12967a04bbbff78a5b56d968d;hpb=b555a215bf6727449dd7415504c8de75a5f09661;p=soc.git

diff --git a/src/soc/experiment/sim.py b/src/soc/experiment/sim.py
index 1c725b25..aebb51de 100644
--- a/src/soc/experiment/sim.py
+++ b/src/soc/experiment/sim.py
@@ -1,4 +1,4 @@
-from soc.decoder.power_enums import InternalOp
+from soc.decoder.power_enums import MicrOp
 
 from random import randint, seed
 from copy import deepcopy
@@ -8,16 +8,15 @@ from math import log
 class MemSim:
     def __init__(self, regwid, addrw):
         self.regwid = regwid
-        self.ddepth = 1 # regwid//8
-        depth = (1<<addrw) // self.ddepth
+        self.ddepth = 1  # regwid//8
+        depth = (1 << addrw) // self.ddepth
         self.mem = list(range(0, depth))
 
     def ld(self, addr):
-        return self.mem[addr>>self.ddepth]
+        return self.mem[addr >> self.ddepth]
 
     def st(self, addr, data):
-        self.mem[addr>>self.ddepth] = data & ((1<<self.regwid)-1)
-
+        self.mem[addr >> self.ddepth] = data & ((1 << self.regwid)-1)
 
 
 IADD = 0
@@ -36,18 +35,18 @@ class RegSim:
         self.regs = [0] * nregs
 
     def op(self, op, op_imm, imm, src1, src2, dest):
-        print ("regsim op src1, src2", op, op_imm, imm, src1, src2, dest)
+        print("regsim op src1, src2", op, op_imm, imm, src1, src2, dest)
         maxbits = (1 << self.rwidth) - 1
         src1 = self.regs[src1] & maxbits
         if op_imm:
             src2 = imm
         else:
             src2 = self.regs[src2] & maxbits
-        if op == InternalOp.OP_ADD:
+        if op == MicrOp.OP_ADD:
             val = src1 + src2
-        elif op == InternalOp.OP_MUL_L64:
+        elif op == MicrOp.OP_MUL_L64:
             val = src1 * src2
-            print ("mul src1, src2", src1, src2, val)
+            print("mul src1, src2", src1, src2, val)
         elif op == ISUB:
             val = src1 - src2
         elif op == ISHF:
@@ -61,13 +60,13 @@ class RegSim:
         elif op == IBNE:
             val = int(src1 != src2)
         else:
-            return 0 # LD/ST TODO
+            return 0  # LD/ST TODO
         val &= maxbits
         self.setval(dest, val)
         return val
 
     def setval(self, dest, val):
-        print ("sim setval", dest, hex(val))
+        print("sim setval", dest, hex(val))
         self.regs[dest] = val
 
     def dump(self, dut):
@@ -83,4 +82,3 @@ class RegSim:
                 print("reg %d expected %x received %x\n" % (i, val, reg))
                 yield from self.dump(dut)
                 assert False
-