X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fsoc%2Fexperiment%2Ftest%2Ftest_compalu_multi.py;h=97eb635f2f2c59d6a722c898b2bd6a3ac49a26a2;hb=65c43ae4c522d129742046eb2e1395ce27d48a09;hp=af79aa28b211fc5ac7e2e3dc405a0710eac54bdc;hpb=c38324645adffec90f6564c5d54b158b166ecd07;p=soc.git diff --git a/src/soc/experiment/test/test_compalu_multi.py b/src/soc/experiment/test/test_compalu_multi.py index af79aa28..97eb635f 100644 --- a/src/soc/experiment/test/test_compalu_multi.py +++ b/src/soc/experiment/test/test_compalu_multi.py @@ -10,21 +10,19 @@ its result(s) have been successfully stored in the regfile(s) Documented at http://libre-soc.org/3d_gpu/architecture/compunit """ +from soc.experiment.alu_fsm import Shifter, CompFSMOpSubset +from soc.fu.alu.alu_input_record import CompALUOpSubset +from soc.experiment.alu_hier import ALU, DummyALU +from soc.experiment.compalu_multi import MultiCompUnit +from soc.decoder.power_enums import MicrOp +from nmigen import Module +from nmigen.cli import rtlil cxxsim = False if cxxsim: from nmigen.sim.cxxsim import Simulator, Settle else: from nmigen.back.pysim import Simulator, Settle -from nmigen.cli import rtlil -from nmigen import Module - -from soc.decoder.power_enums import MicrOp - -from soc.experiment.compalu_multi import MultiCompUnit -from soc.experiment.alu_hier import ALU, DummyALU -from soc.fu.alu.alu_input_record import CompALUOpSubset -from soc.experiment.alu_fsm import Shifter, CompFSMOpSubset def wrap(process): def wrapper(): @@ -33,7 +31,7 @@ def wrap(process): def op_sim_fsm(dut, a, b, direction): - print ("op_sim_fsm", a, b, direction) + print("op_sim_fsm", a, b, direction) yield dut.issue_i.eq(0) yield yield dut.src_i[0].eq(a) @@ -44,31 +42,31 @@ def op_sim_fsm(dut, a, b, direction): yield dut.issue_i.eq(0) yield - yield dut.rd.go.eq(0b11) + yield dut.rd.go_i.eq(0b11) while True: yield - rd_rel_o = yield dut.rd.rel - print ("rd_rel", rd_rel_o) + rd_rel_o = yield dut.rd.rel_o + print("rd_rel", rd_rel_o) if rd_rel_o: break - yield dut.rd.go.eq(0) + yield dut.rd.go_i.eq(0) - req_rel_o = yield dut.wr.rel + req_rel_o = yield dut.wr.rel_o result = yield dut.data_o - print ("req_rel", req_rel_o, result) + print("req_rel", req_rel_o, result) while True: - req_rel_o = yield dut.wr.rel + req_rel_o = yield dut.wr.rel_o result = yield dut.data_o - print ("req_rel", req_rel_o, result) + print("req_rel", req_rel_o, result) if req_rel_o: break yield - yield dut.wr.go[0].eq(1) + yield dut.wr.go_i[0].eq(1) yield Settle() result = yield dut.data_o yield - print ("result", result) - yield dut.wr.go[0].eq(0) + print("result", result) + yield dut.wr.go_i[0].eq(0) yield return result @@ -79,7 +77,7 @@ def op_sim(dut, a, b, op, inv_a=0, imm=0, imm_ok=0, zero_a=0): yield dut.src_i[0].eq(a) yield dut.src_i[1].eq(b) yield dut.oper_i.insn_type.eq(op) - yield dut.oper_i.invert_a.eq(inv_a) + yield dut.oper_i.invert_in.eq(inv_a) yield dut.oper_i.imm_data.imm.eq(imm) yield dut.oper_i.imm_data.imm_ok.eq(imm_ok) yield dut.oper_i.zero_a.eq(zero_a) @@ -88,45 +86,45 @@ def op_sim(dut, a, b, op, inv_a=0, imm=0, imm_ok=0, zero_a=0): yield dut.issue_i.eq(0) yield if not imm_ok or not zero_a: - yield dut.rd.go.eq(0b11) + yield dut.rd.go_i.eq(0b11) while True: yield - rd_rel_o = yield dut.rd.rel - print ("rd_rel", rd_rel_o) + rd_rel_o = yield dut.rd.rel_o + print("rd_rel", rd_rel_o) if rd_rel_o: break - yield dut.rd.go.eq(0) + yield dut.rd.go_i.eq(0) else: - print ("no go rd") + print("no go rd") if len(dut.src_i) == 3: - yield dut.rd.go.eq(0b100) + yield dut.rd.go_i.eq(0b100) while True: yield - rd_rel_o = yield dut.rd.rel - print ("rd_rel", rd_rel_o) + rd_rel_o = yield dut.rd.rel_o + print("rd_rel", rd_rel_o) if rd_rel_o: break - yield dut.rd.go.eq(0) + yield dut.rd.go_i.eq(0) else: - print ("no 3rd rd") + print("no 3rd rd") - req_rel_o = yield dut.wr.rel + req_rel_o = yield dut.wr.rel_o result = yield dut.data_o - print ("req_rel", req_rel_o, result) + print("req_rel", req_rel_o, result) while True: - req_rel_o = yield dut.wr.rel + req_rel_o = yield dut.wr.rel_o result = yield dut.data_o - print ("req_rel", req_rel_o, result) + print("req_rel", req_rel_o, result) if req_rel_o: break yield - yield dut.wr.go[0].eq(1) + yield dut.wr.go_i[0].eq(1) yield Settle() result = yield dut.data_o yield - print ("result", result) - yield dut.wr.go[0].eq(0) + print("result", result) + yield dut.wr.go_i[0].eq(0) yield return result @@ -144,23 +142,22 @@ def scoreboard_sim_fsm(dut): def scoreboard_sim_dummy(dut): result = yield from op_sim(dut, 5, 2, MicrOp.OP_NOP, inv_a=0, - imm=8, imm_ok=1) + imm=8, imm_ok=1) assert result == 5, result result = yield from op_sim(dut, 9, 2, MicrOp.OP_NOP, inv_a=0, - imm=8, imm_ok=1) + imm=8, imm_ok=1) assert result == 9, result - def scoreboard_sim(dut): # zero (no) input operands test result = yield from op_sim(dut, 5, 2, MicrOp.OP_ADD, zero_a=1, - imm=8, imm_ok=1) + imm=8, imm_ok=1) assert result == 8 result = yield from op_sim(dut, 5, 2, MicrOp.OP_ADD, inv_a=0, - imm=8, imm_ok=1) + imm=8, imm_ok=1) assert result == 13 result = yield from op_sim(dut, 5, 2, MicrOp.OP_ADD) @@ -288,7 +285,7 @@ class CompUnitParallelTest: # at the same time, present the operation yield self.dut.oper_i.insn_type.eq(self.op) - yield self.dut.oper_i.invert_a.eq(self.inv_a) + yield self.dut.oper_i.invert_in.eq(self.inv_a) yield self.dut.oper_i.imm_data.imm.eq(self.imm) yield self.dut.oper_i.imm_data.imm_ok.eq(self.imm_ok) yield self.dut.oper_i.zero_a.eq(self.zero_a) @@ -313,7 +310,7 @@ class CompUnitParallelTest: # note: rdmaskn must be held, while busy_o is active # TODO: deactivate rdmaskn when the busy_o cycle ends yield self.dut.oper_i.insn_type.eq(0) - yield self.dut.oper_i.invert_a.eq(0) + yield self.dut.oper_i.invert_in.eq(0) yield self.dut.oper_i.imm_data.imm.eq(0) yield self.dut.oper_i.imm_data.imm_ok.eq(0) yield self.dut.oper_i.zero_a.eq(0) @@ -349,7 +346,7 @@ class CompUnitParallelTest: if issue_i: break # issue_i has not risen yet, so rd must keep low - rel = yield self.dut.rd.rel[rd_idx] + rel = yield self.dut.rd.rel_o[rd_idx] assert not rel yield @@ -363,24 +360,24 @@ class CompUnitParallelTest: return # issue_i has risen. rel must rise on the next cycle - rel = yield self.dut.rd.rel[rd_idx] + rel = yield self.dut.rd.rel_o[rd_idx] assert not rel # stall for additional cycles. Check that rel doesn't fall on its own for n in range(self.RD_GO_DELAY[rd_idx]): yield - rel = yield self.dut.rd.rel[rd_idx] + rel = yield self.dut.rd.rel_o[rd_idx] assert rel # Before asserting "go", make sure "rel" has risen. # The use of Settle allows "go" to be set combinatorially, # rising on the same cycle as "rel". yield Settle() - rel = yield self.dut.rd.rel[rd_idx] + rel = yield self.dut.rd.rel_o[rd_idx] assert rel # assert go for one cycle, passing along the operand value - yield self.dut.rd.go[rd_idx].eq(1) + yield self.dut.rd.go_i[rd_idx].eq(1) yield self.dut.src_i[rd_idx].eq(self.operands[rd_idx]) # check that the operand was sent to the alu # TODO: Properly check the alu protocol @@ -390,17 +387,17 @@ class CompUnitParallelTest: yield # rel must keep high, since go was inactive in the last cycle - rel = yield self.dut.rd.rel[rd_idx] + rel = yield self.dut.rd.rel_o[rd_idx] assert rel # finish the go one-clock pulse - yield self.dut.rd.go[rd_idx].eq(0) + yield self.dut.rd.go_i[rd_idx].eq(0) yield self.dut.src_i[rd_idx].eq(0) yield # rel must have gone low in response to go being high # on the previous cycle - rel = yield self.dut.rd.rel[rd_idx] + rel = yield self.dut.rd.rel_o[rd_idx] assert not rel self.rd_complete[rd_idx] = True @@ -433,9 +430,9 @@ def test_compunit_regspec2_fsm(): inspec = [('INT', 'a', '0:15'), ('INT', 'b', '0:15'), - ] - outspec = [('INT', 'o', '0:15'), ] + outspec = [('INT', 'o', '0:15'), + ] regspec = (inspec, outspec) @@ -459,7 +456,7 @@ def test_compunit_regspec3(): ('INT', 'b', '0:15'), ('INT', 'c', '0:15')] outspec = [('INT', 'o', '0:15'), - ] + ] regspec = (inspec, outspec) @@ -482,7 +479,7 @@ def test_compunit_regspec1(): inspec = [('INT', 'a', '0:15'), ('INT', 'b', '0:15')] outspec = [('INT', 'o', '0:15'), - ] + ] regspec = (inspec, outspec)