X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fsoc%2Ffu%2FREADME.md;fp=src%2Fsoc%2Ffu%2FREADME.md;h=dc09399f5f1af1307b6236d29140af2590dc3684;hb=387adb06229a96bcba9aee4c470d09244fda77d2;hp=fad4daef7856bd55d9555788cff51232ae24227c;hpb=e2f74e92db8663df65d5fb286d951bc7bf92edc5;p=soc.git

diff --git a/src/soc/fu/README.md b/src/soc/fu/README.md
index fad4daef..dc09399f 100644
--- a/src/soc/fu/README.md
+++ b/src/soc/fu/README.md
@@ -8,6 +8,18 @@ as follows:
 * XXX_input_record.py: a PowerISA decoded instruction subset for this pipeline
 * pipeline.py: the actual pipeline chain, which brings all stages together
 
+# Computation Units
+
+A subdirectory named compunits contains the 6600 style "Comp Units".
+These are pipeline managers whose sole job is to monitor the operation
+in its entirety from start to finish, including receiving of all
+operands and the storage of all results. AT NO TIME does a Comp Unit
+"abandon" data to a pipeline.
+
+Each pipeline is given a Como Umit frontend.  The base class uses regsoecs
+to construct the required latches in order to send and receive dsta to
+and from the required Register Files.
+
 # Common files
 
 * regspec.py: the register specification API.  used by each pipe_data.py