X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fsoc%2Ffu%2Fcommon_input_stage.py;h=53e023ad6bb68d289bacccc9f5f627936961753e;hb=9b9e1fa911327bb4e373031e56f45581bcb0f1dd;hp=238c8d57a9dec7907d497701597f01e419d90ebb;hpb=78183662a64e0be018ad22de14f323c28e611f76;p=soc.git

diff --git a/src/soc/fu/common_input_stage.py b/src/soc/fu/common_input_stage.py
index 238c8d57..53e023ad 100644
--- a/src/soc/fu/common_input_stage.py
+++ b/src/soc/fu/common_input_stage.py
@@ -3,8 +3,8 @@
 # generation for subtraction, should happen here
 from nmigen import (Module, Signal)
 from nmutil.pipemodbase import PipeModBase
-from soc.decoder.power_enums import MicrOp
-from soc.decoder.power_enums import CryIn
+from openpower.decoder.power_enums import MicrOp
+from openpower.decoder.power_enums import CryIn
 
 
 class CommonInputStage(PipeModBase):
@@ -31,7 +31,9 @@ class CommonInputStage(PipeModBase):
         else:
             comb += a.eq(self.i.a)
 
-        comb += self.o.a.eq(a)
+        # SV zeroing on predicate source zeros the input
+        with m.If(~op.sv_pred_sz):
+            comb += self.o.a.eq(a)
 
         ##### operand B #####
 
@@ -46,7 +48,9 @@ class CommonInputStage(PipeModBase):
         else:
             comb += b.eq(self.i.b)
 
-        comb += self.o.b.eq(b)
+        # SV zeroing on predicate source zeros the input
+        with m.If(~op.sv_pred_sz):
+            comb += self.o.b.eq(b)
 
         ##### carry-in #####
 
@@ -66,8 +70,7 @@ class CommonInputStage(PipeModBase):
         ##### sticky overflow and context (both pass-through) #####
 
         if hasattr(self.o, "xer_so"): # hack (for now - for LogicalInputData)
-            with m.If(op.oe.oe_ok):
-                comb += self.o.xer_so.eq(self.i.xer_so)
+            comb += self.o.xer_so.eq(self.i.xer_so)
         comb += self.o.ctx.eq(self.i.ctx)
 
         return m