X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fsoc%2Ffu%2Fcommon_output_stage.py;h=dc17410af790998086d38643518860aab0406cd3;hb=80252d01401180b54731a8dea310d4d63bcd2e34;hp=530db3ac0120fe2dd2bd28b493405378c1619df4;hpb=cd088b785ee6e4a9fd9e5c1b87c63a13e9e7386b;p=soc.git

diff --git a/src/soc/fu/common_output_stage.py b/src/soc/fu/common_output_stage.py
index 530db3ac..dc17410a 100644
--- a/src/soc/fu/common_output_stage.py
+++ b/src/soc/fu/common_output_stage.py
@@ -3,7 +3,7 @@
 from nmigen import (Module, Signal, Cat, Const)
 from nmutil.pipemodbase import PipeModBase
 from ieee754.part.partsig import PartitionedSignal
-from soc.decoder.power_enums import MicrOp
+from openpower.decoder.power_enums import MicrOp
 
 
 class CommonOutputStage(PipeModBase):
@@ -21,23 +21,33 @@ class CommonOutputStage(PipeModBase):
         #     has been pass-through just to get it into CR0
         # in case (1) we don't *have* an xer_so output so put xer_so *input*
         # into CR0.
+        xer_so_i = self.i.xer_so.data[0]
         if hasattr(self.o, "xer_so"):
             xer_so_o = self.o.xer_so.data[0]
-        else:
-            xer_so_o = self.i.xer_so.data[0]
-
-        # op requests inversion of the output...
-        o = Signal.like(self.i.o)
-        if hasattr(op, "invert_out"): # ... optionally
-            with m.If(op.invert_out):
-                comb += o.eq(~self.i.o.data)
+            so = Signal(reset_less=True)
+            oe = Signal(reset_less=True)
+            comb += oe.eq(op.oe.oe & op.oe.ok)
+            with m.If(oe):
+                comb += so.eq(xer_so_o)
             with m.Else():
-                comb += o.eq(self.i.o.data)
+                comb += so.eq(xer_so_i)
         else:
-            comb += o.eq(self.i.o.data) # ... no inversion
+            so = xer_so_i
+
+        with m.If(~op.sv_pred_dz): # when SVP64 zeroing is set, output is zero
+            # op requests inversion of the output...
+            o = Signal.like(self.i.o)
+            if hasattr(op, "invert_out"): # ... optionally
+                with m.If(op.invert_out):
+                    comb += o.eq(~self.i.o.data)
+                with m.Else():
+                    comb += o.eq(self.i.o.data)
+            else:
+                comb += o.eq(self.i.o.data) # ... no inversion
 
         # target register if 32-bit is only the 32 LSBs
         # XXX ah.  right.  this needs to be done only if the *mode* is 32-bit
+        # (an MSR bit)
         # see https://bugs.libre-soc.org/show_bug.cgi?id=424
         target = Signal(64, reset_less=True)
         #with m.If(op.is_32bit):
@@ -68,32 +78,22 @@ class CommonOutputStage(PipeModBase):
 
         comb += is_cmp.eq(op.insn_type == MicrOp.OP_CMP)
         comb += is_cmpeqb.eq(op.insn_type == MicrOp.OP_CMPEQB)
-        # nope - if *processor* mode is 32-bit
-        #with m.If(op.is_32bit):
-        #    comb += msb_test.eq(target[-1] ^ is_cmp) # 64-bit MSB
-        #with m.Else():
-        #    comb += msb_test.eq(target[31] ^ is_cmp) # 32-bit MSB
-        comb += msb_test.eq(target[-1]) # 64-bit MSB
+
+        comb += msb_test.eq(target[-1]) # 64-bit MSB, TODO 32-bit MSB
         comb += is_nzero.eq(target.bool())
-        with m.If(is_cmp): # invert pos/neg tests
-            comb += is_positive.eq(msb_test)
-            comb += is_negative.eq(is_nzero & ~msb_test)
-        with m.Else():
-            comb += is_negative.eq(msb_test)
-            comb += is_positive.eq(is_nzero & ~msb_test)
+        comb += is_negative.eq(msb_test)
+        comb += is_positive.eq(is_nzero & ~msb_test)
 
-        with m.If(is_cmpeqb):
+        with m.If(is_cmpeqb | is_cmp):
             comb += cr0.eq(self.i.cr0.data)
         with m.Else():
-            comb += cr0.eq(Cat(xer_so_o, ~is_nzero, is_positive, is_negative))
+            comb += cr0.eq(Cat(so, ~is_nzero, is_positive, is_negative))
 
         # copy out [inverted?] output, cr0, and context out
         comb += self.o.o.data.eq(o)
         comb += self.o.o.ok.eq(self.i.o.ok)
-        # CR0 to be set
-        comb += self.o.cr0.data.eq(cr0)
+        comb += self.o.cr0.data.eq(cr0) # CR0 to be set
         comb += self.o.cr0.ok.eq(op.write_cr0)
-        # context
-        comb += self.o.ctx.eq(self.i.ctx)
+        comb += self.o.ctx.eq(self.i.ctx) # context
 
         return m