X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fsoc%2Ffu%2Fcommon_output_stage.py;h=dc17410af790998086d38643518860aab0406cd3;hb=80252d01401180b54731a8dea310d4d63bcd2e34;hp=e5cf3a308506e23207e82acae6e4c4f16eea1807;hpb=3ba07d7528444bc085778bc7f643352e866f7a88;p=soc.git

diff --git a/src/soc/fu/common_output_stage.py b/src/soc/fu/common_output_stage.py
index e5cf3a30..dc17410a 100644
--- a/src/soc/fu/common_output_stage.py
+++ b/src/soc/fu/common_output_stage.py
@@ -34,18 +34,20 @@ class CommonOutputStage(PipeModBase):
         else:
             so = xer_so_i
 
-        # op requests inversion of the output...
-        o = Signal.like(self.i.o)
-        if hasattr(op, "invert_out"): # ... optionally
-            with m.If(op.invert_out):
-                comb += o.eq(~self.i.o.data)
-            with m.Else():
-                comb += o.eq(self.i.o.data)
-        else:
-            comb += o.eq(self.i.o.data) # ... no inversion
+        with m.If(~op.sv_pred_dz): # when SVP64 zeroing is set, output is zero
+            # op requests inversion of the output...
+            o = Signal.like(self.i.o)
+            if hasattr(op, "invert_out"): # ... optionally
+                with m.If(op.invert_out):
+                    comb += o.eq(~self.i.o.data)
+                with m.Else():
+                    comb += o.eq(self.i.o.data)
+            else:
+                comb += o.eq(self.i.o.data) # ... no inversion
 
         # target register if 32-bit is only the 32 LSBs
         # XXX ah.  right.  this needs to be done only if the *mode* is 32-bit
+        # (an MSR bit)
         # see https://bugs.libre-soc.org/show_bug.cgi?id=424
         target = Signal(64, reset_less=True)
         #with m.If(op.is_32bit):
@@ -77,7 +79,7 @@ class CommonOutputStage(PipeModBase):
         comb += is_cmp.eq(op.insn_type == MicrOp.OP_CMP)
         comb += is_cmpeqb.eq(op.insn_type == MicrOp.OP_CMPEQB)
 
-        comb += msb_test.eq(target[-1]) # 64-bit MSB
+        comb += msb_test.eq(target[-1]) # 64-bit MSB, TODO 32-bit MSB
         comb += is_nzero.eq(target.bool())
         comb += is_negative.eq(msb_test)
         comb += is_positive.eq(is_nzero & ~msb_test)
@@ -90,10 +92,8 @@ class CommonOutputStage(PipeModBase):
         # copy out [inverted?] output, cr0, and context out
         comb += self.o.o.data.eq(o)
         comb += self.o.o.ok.eq(self.i.o.ok)
-        # CR0 to be set
-        comb += self.o.cr0.data.eq(cr0)
+        comb += self.o.cr0.data.eq(cr0) # CR0 to be set
         comb += self.o.cr0.ok.eq(op.write_cr0)
-        # context
-        comb += self.o.ctx.eq(self.i.ctx)
+        comb += self.o.ctx.eq(self.i.ctx) # context
 
         return m