X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fsoc%2Ffu%2Fcompunits%2Ftest%2Ftest_compunit.py;h=1265ba94ae1c785963a4a0ad585da4dca083fb89;hb=2565a10fa87f402b2bb433d641228d8f9067d444;hp=62d2f2aaa9e4329c4ae1a75857038e5f4525c72e;hpb=3924f545019e566c5af1d7d067286ee374a3c7ed;p=soc.git

diff --git a/src/soc/fu/compunits/test/test_compunit.py b/src/soc/fu/compunits/test/test_compunit.py
index 62d2f2aa..1265ba94 100644
--- a/src/soc/fu/compunits/test/test_compunit.py
+++ b/src/soc/fu/compunits/test/test_compunit.py
@@ -1,19 +1,15 @@
-from nmigen import Module, Signal
+from nmigen import Module, Signal, ResetSignal
 from nmigen.back.pysim import Simulator, Delay, Settle
-from nmigen.test.utils import FHDLTestCase
+from nmutil.formaltest import FHDLTestCase
 from nmigen.cli import rtlil
 import unittest
-from soc.decoder.isa.caller import ISACaller, special_sprs
 from soc.decoder.power_decoder import (create_pdecode)
 from soc.decoder.power_decoder2 import (PowerDecode2)
-from soc.decoder.power_enums import (XER_bits, Function, InternalOp)
-from soc.decoder.selectable_int import SelectableInt
-from soc.simulator.program import Program
+from soc.decoder.power_enums import Function
 from soc.decoder.isa.all import ISA
 
-from soc.fu.alu.test.test_pipe_caller import TestCase, ALUTestCase, test_data
 from soc.experiment.compalu_multi import find_ok # hack
-import random
+
 
 def set_cu_input(cu, idx, data):
     rdop = cu.get_in_name(idx)
@@ -33,6 +29,7 @@ def set_cu_input(cu, idx, data):
         print ("rd_rel %d wait HI" % idx, rd_rel_o)
         yield
     yield cu.rd.go[idx].eq(0)
+    yield cu.src_i[idx].eq(0)
 
 
 def get_cu_output(cu, idx, code):
@@ -59,6 +56,7 @@ def get_cu_output(cu, idx, code):
     yield
     yield cu.wr.go[idx].eq(0)
     print ("result", repr(code), idx, wrop, wrok, hex(result))
+
     return result
 
 
@@ -77,6 +75,16 @@ def set_operand(cu, dec2, sim):
 
 def get_cu_outputs(cu, code):
     res = {}
+    wrmask = yield cu.wrmask
+    print ("get_cu_outputs", cu.n_dst, wrmask)
+    if not wrmask: # no point waiting (however really should doublecheck wr.rel)
+        return {}
+    # wait for at least one result
+    while True:
+        wr_rel_o = yield cu.wr.rel
+        if wr_rel_o:
+            break
+        yield
     for i in range(cu.n_dst):
         wr_rel_o = yield cu.wr.rel[i]
         if wr_rel_o:
@@ -95,13 +103,6 @@ def get_inp_indexed(cu, inp):
             res[i] = inp[wrop]
     return res
 
-def get_cu_rd_mask(n_src, inp):
-    mask = 0
-    for i in range(n_src):
-        if i in inp:
-            mask |= (1<<i)
-    return mask
-
 
 class TestRunner(FHDLTestCase):
     def __init__(self, test_data, fukls, iodef, funit):
@@ -119,7 +120,15 @@ class TestRunner(FHDLTestCase):
         pdecode = create_pdecode()
 
         m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
-        m.submodules.cu = cu = self.fukls()
+        if self.funit == Function.LDST:
+            from soc.experiment.l0_cache import TstL0CacheBuffer
+            m.submodules.l0 = l0 = TstL0CacheBuffer(n_units=1, regwid=64)
+            pi = l0.l0.dports[0].pi
+            m.submodules.cu = cu = self.fukls(pi, awid=4)
+            m.d.comb += cu.ad.go.eq(cu.ad.rel) # link addr-go direct to rel
+            m.d.comb += cu.st.go.eq(cu.st.rel) # link store-go direct to rel
+        else:
+            m.submodules.cu = cu = self.fukls()
 
         comb += pdecode2.dec.raw_opcode_in.eq(instruction)
         sim = Simulator(m)
@@ -134,10 +143,21 @@ class TestRunner(FHDLTestCase):
                 print(test.name)
                 program = test.program
                 self.subTest(test.name)
-                sim = ISA(pdecode2, test.regs, test.sprs, 0)
+                print ("test", test.name, test.mem)
+                sim = ISA(pdecode2, test.regs, test.sprs, test.cr, test.mem,
+                          test.msr)
                 gen = program.generate_instructions()
                 instructions = list(zip(gen, program.assembly.splitlines()))
 
+                # initialise memory
+                if self.funit == Function.LDST:
+                    mem = l0.mem.mem
+                    for i in range(mem.depth//2):
+                        data = sim.mem.ld(i*16, 8)
+                        data1 = sim.mem.ld(i*16+8, 8)
+                        yield mem._array[i].eq(data | (data1<<32))
+                    print ("init mem", mem.depth, mem.width, mem)
+
                 index = sim.pc.CIA.value//4
                 while index < len(instructions):
                     ins, code = instructions[index]
@@ -150,7 +170,8 @@ class TestRunner(FHDLTestCase):
                     yield instruction.eq(ins)          # raw binary instr.
                     yield Settle()
                     fn_unit = yield pdecode2.e.fn_unit
-                    self.assertEqual(fn_unit, self.funit.value)
+                    fuval = self.funit.value
+                    self.assertEqual(fn_unit & fuval, fuval)
 
                     # set operand and get inputs
                     yield from set_operand(cu, pdecode2, sim)
@@ -158,7 +179,9 @@ class TestRunner(FHDLTestCase):
                     inp = get_inp_indexed(cu, iname)
 
                     # reset read-operand mask
-                    rdmask = get_cu_rd_mask(cu.n_src, inp)
+                    rdmask = pdecode2.rdflags(cu)
+                    #print ("hardcoded rdmask", cu.rdflags(pdecode2.e))
+                    #print ("decoder rdmask", rdmask)
                     yield cu.rdmaskn.eq(~rdmask)
 
                     # reset write-operand mask
@@ -167,13 +190,18 @@ class TestRunner(FHDLTestCase):
                         fname = find_ok(wrok.fields)
                         yield getattr(wrok, fname).eq(0)
 
+                    yield Settle()
+
                     # set inputs into CU
                     rd_rel_o = yield cu.rd.rel
                     wr_rel_o = yield cu.wr.rel
                     print ("before inputs, rd_rel, wr_rel: ",
                             bin(rd_rel_o), bin(wr_rel_o))
+                    assert wr_rel_o == 0, "wr.rel %s must be zero. "\
+                                "previous instr not written all regs\n"\
+                                "respec %s" % \
+                                (bin(wr_rel_o), cu.rwid[1])
                     yield from set_cu_inputs(cu, inp)
-                    yield
                     rd_rel_o = yield cu.rd.rel
                     wr_rel_o = yield cu.wr.rel
                     wrmask = yield cu.wrmask
@@ -185,14 +213,52 @@ class TestRunner(FHDLTestCase):
                     yield from sim.call(opname)
                     index = sim.pc.CIA.value//4
 
+                    yield Settle()
                     # get all outputs (one by one, just "because")
                     res = yield from get_cu_outputs(cu, code)
+                    wrmask = yield cu.wrmask
+                    rd_rel_o = yield cu.rd.rel
+                    wr_rel_o = yield cu.wr.rel
+                    print ("after got outputs, rd_rel, wr_rel, wrmask: ",
+                            bin(rd_rel_o), bin(wr_rel_o), bin(wrmask))
+
+                    # wait for busy to go low
+                    while True:
+                        busy_o = yield cu.busy_o
+                        print ("busy", busy_o)
+                        if not busy_o:
+                            break
+                        yield
 
                     yield from self.iodef.check_cu_outputs(res, pdecode2,
                                                             sim, code)
 
+                    # sigh.  hard-coded.  test memory
+                    if self.funit == Function.LDST:
+                        mem = l0.mem.mem
+                        print ("sim mem dump")
+                        for k, v in sim.mem.mem.items():
+                            print ("    %6x %016x" % (k, v))
+                        print ("nmigen mem dump")
+                        for i in range(mem.depth//2):
+                            actual_mem = yield mem._array[i]
+                            print ("    %6i %032x" % (i*2, actual_mem))
+
+                        for i in range(mem.depth//2):
+                            data = sim.mem.ld(i*16, 8)
+                            data1 = sim.mem.ld(i*16+8, 8)
+                            expected_mem = (data | (data1<<32))
+                            actual_mem = yield mem._array[i]
+                            self.assertEqual(expected_mem, actual_mem,
+                                    "%s %d %x %x" % (code, i,
+                                                     expected_mem, actual_mem))
+
+
         sim.add_sync_process(process)
-        with sim.write_vcd("simulator.vcd", "simulator.gtkw",
+
+        name = self.funit.name.lower()
+        with sim.write_vcd("%s_simulator.vcd" % name,
+                           "%s_simulator.gtkw" % name,
                             traces=[]):
             sim.run()