X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fsoc%2Ffu%2Fdiv%2Fcore_stages.py;fp=src%2Fsoc%2Ffu%2Fdiv%2Fcore_stages.py;h=fdbe8659583b01a2073db5e01aae137c965286fa;hb=c25d3e23de63d0cab676a76a1bb3e497640cc2a6;hp=3bbde7dba509721545a51a6d223974091db3fc28;hpb=61ab3fd7b53c5c51baca1d61837a3270c0c9f589;p=soc.git

diff --git a/src/soc/fu/div/core_stages.py b/src/soc/fu/div/core_stages.py
index 3bbde7db..fdbe8659 100644
--- a/src/soc/fu/div/core_stages.py
+++ b/src/soc/fu/div/core_stages.py
@@ -3,14 +3,14 @@
 
 from nmigen import (Module, Signal, Cat, Repl, Mux, Const, Array)
 from nmutil.pipemodbase import PipeModBase
-from soc.fu.logical.pipe_data import LogicalInputData
-from soc.fu.alu.pipe_data import ALUOutputData
 from ieee754.part.partsig import PartitionedSignal
 from soc.decoder.power_enums import InternalOp
 
 from soc.decoder.power_fields import DecodeFields
 from soc.decoder.power_fieldsn import SignalBitRange
-from soc.fu.div.pipe_data import CoreInputData, CoreInterstageData, CoreOutputData
+from soc.fu.div.pipe_data import (CoreInputData,
+                                  CoreInterstageData,
+                                  CoreOutputData)
 from ieee754.div_rem_sqrt_rsqrt.core import (DivPipeCoreSetupStage,
                                              DivPipeCoreCalculateStage,
                                              DivPipeCoreFinalStage)