X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fsoc%2Ffu%2Fdiv%2Fcore_stages.py;h=9f63a63117ac5e0d4a72f4e7d0dc901d721fd504;hb=HEAD;hp=fc1d7520e0b094a0b8c32da2d026bd65c9a7cb15;hpb=401bdf070c25cfca2e7907007df58020ef88faa8;p=soc.git

diff --git a/src/soc/fu/div/core_stages.py b/src/soc/fu/div/core_stages.py
index fc1d7520..e271876b 100644
--- a/src/soc/fu/div/core_stages.py
+++ b/src/soc/fu/div/core_stages.py
@@ -3,11 +3,11 @@
 
 from nmigen import (Module, Signal, Cat, Repl, Mux, Const, Array)
 from nmutil.pipemodbase import PipeModBase
-from ieee754.part.partsig import PartitionedSignal
-from soc.decoder.power_enums import MicrOp
+from ieee754.part.partsig import SimdSignal
+from openpower.decoder.power_enums import MicrOp
 
-from soc.decoder.power_fields import DecodeFields
-from soc.decoder.power_fieldsn import SignalBitRange
+from openpower.decoder.power_fields import DecodeFields
+from openpower.decoder.power_fieldsn import SignalBitRange
 from soc.fu.div.pipe_data import (CoreInputData,
                                   CoreInterstageData,
                                   CoreOutputData)