X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fsoc%2Ffu%2Flogical%2Fpipe_data.py;h=ba24ce6d4bbf706d49c1a1c6f26d4b000053e770;hb=93fb5e930101a3bbb317e6180fc598f56b43cb9c;hp=9ed7252f4c36715b0f061c83e575086bfeb482d9;hpb=407f41392acaec1902e75cde2953c9c8f5d0692c;p=soc.git

diff --git a/src/soc/fu/logical/pipe_data.py b/src/soc/fu/logical/pipe_data.py
index 9ed7252f..ba24ce6d 100644
--- a/src/soc/fu/logical/pipe_data.py
+++ b/src/soc/fu/logical/pipe_data.py
@@ -1,29 +1,60 @@
-from nmigen import Signal, Const
+from nmigen import Signal, Const, Cat
 from ieee754.fpcommon.getop import FPPipeContext
-from soc.fu.alu.pipe_data import IntegerData
+from soc.fu.pipe_data import IntegerData
+from soc.decoder.power_decoder2 import Data
+from soc.fu.alu.pipe_data import ALUOutputData, CommonPipeSpec
+from soc.fu.logical.logical_input_record import CompLogicalOpSubset
 
 
 class LogicalInputData(IntegerData):
     regspec = [('INT', 'a', '0:63'),
-               ('INT', 'rb', '0:63'),
-               ('XER', 'xer_so', '32'),
-               ('XER', 'xer_ca', '34,45')]
+               ('INT', 'b', '0:63'),
+               ]
     def __init__(self, pspec):
         super().__init__(pspec)
         self.a = Signal(64, reset_less=True) # RA
         self.b = Signal(64, reset_less=True) # RB/immediate
-        self.xer_so = Signal(reset_less=True)    # XER bit 32: SO
-        self.xer_ca = Signal(2, reset_less=True) # XER bit 34/45: CA/CA32
 
     def __iter__(self):
         yield from super().__iter__()
         yield self.a
         yield self.b
-        yield self.xer_ca
-        yield self.xer_so
 
     def eq(self, i):
         lst = super().eq(i)
         return lst + [self.a.eq(i.a), self.b.eq(i.b),
+                       ]
+
+
+class LogicalOutputData(IntegerData):
+    regspec = [('INT', 'o', '0:63'),
+               ('CR', 'cr0', '0:3'),
+               ('XER', 'xer_ca', '34,45'),
+               ]
+    def __init__(self, pspec):
+        super().__init__(pspec)
+        self.o = Data(64, name="stage_o")  # RT
+        self.cr0 = Data(4, name="cr0")
+        self.xer_ca = Data(2, name="xer_co") # bit0: ca, bit1: ca32
+
+    def __iter__(self):
+        yield from super().__iter__()
+        yield self.o
+        yield self.xer_ca
+        yield self.cr0
+
+    def eq(self, i):
+        lst = super().eq(i)
+        return lst + [self.o.eq(i.o),
                       self.xer_ca.eq(i.xer_ca),
-                      self.xer_so.eq(i.xer_so)]
+                      self.cr0.eq(i.cr0),
+                      ]
+
+
+class LogicalPipeSpec(CommonPipeSpec):
+    regspec = (LogicalInputData.regspec, LogicalOutputData.regspec)
+    opsubsetkls = CompLogicalOpSubset
+    def rdflags(self, e): # in order of regspec
+        reg1_ok = e.read_reg1.ok # RA
+        reg2_ok = e.read_reg2.ok # RB
+        return Cat(reg1_ok, reg2_ok) # RA RB