X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fsoc%2Ffu%2Flogical%2Ftest%2Ftest_pipe_caller.py;h=5df6effc09109b45c399ad7e6c759bc824810e4e;hb=2adbe7711bec6c228e9cb6ffb7c7ef30b1621c8f;hp=997d5a654a68c32a97e4b0c079a6aba7c4f511e6;hpb=575802fa56d7175ebbdc16bb5c493b556dab9c74;p=soc.git diff --git a/src/soc/fu/logical/test/test_pipe_caller.py b/src/soc/fu/logical/test/test_pipe_caller.py index 997d5a65..5df6effc 100644 --- a/src/soc/fu/logical/test/test_pipe_caller.py +++ b/src/soc/fu/logical/test/test_pipe_caller.py @@ -1,23 +1,26 @@ from nmigen import Module, Signal -from nmigen.back.pysim import Simulator, Delay, Settle + +# NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell +# Also, check out the cxxsim nmigen branch, and latest yosys from git +from nmutil.sim_tmp_alternative import Simulator, Settle + from nmutil.formaltest import FHDLTestCase from nmigen.cli import rtlil import unittest -from soc.decoder.isa.caller import ISACaller, special_sprs -from soc.decoder.power_decoder import (create_pdecode) -from soc.decoder.power_decoder2 import (PowerDecode2) -from soc.decoder.power_enums import (XER_bits, Function) -from soc.decoder.selectable_int import SelectableInt -from soc.simulator.program import Program -from soc.decoder.isa.all import ISA -from soc.config.endian import bigendian +from openpower.decoder.power_decoder import create_pdecode +from openpower.decoder.power_decoder2 import PowerDecode2 +from openpower.decoder.power_enums import (XER_bits, Function) +from openpower.decoder.isa.all import ISA +from openpower.endian import bigendian -from soc.fu.test.common import TestCase, ALUHelpers +from openpower.test.common import TestAccumulatorBase, ALUHelpers from soc.fu.logical.pipeline import LogicalBasePipe from soc.fu.logical.pipe_data import LogicalPipeSpec import random +from openpower.test.logical.logical_cases import LogicalTestCase + def get_cu_inputs(dec2, sim): """naming (res) must conform to LogicalFunctionUnit input regspec @@ -26,6 +29,9 @@ def get_cu_inputs(dec2, sim): yield from ALUHelpers.get_sim_int_ra(res, sim, dec2) # RA yield from ALUHelpers.get_sim_int_rb(res, sim, dec2) # RB + yield from ALUHelpers.get_sim_xer_so(res, sim, dec2) # XER.so + + print("alu get_cu_inputs", res) return res @@ -33,131 +39,77 @@ def get_cu_inputs(dec2, sim): def set_alu_inputs(alu, dec2, sim): # TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43 # detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok)) - # and place it into data_i.b + # and place it into i_data.b inp = yield from get_cu_inputs(dec2, sim) + print("set alu inputs", inp) yield from ALUHelpers.set_int_ra(alu, dec2, inp) yield from ALUHelpers.set_int_rb(alu, dec2, inp) + yield from ALUHelpers.set_xer_so(alu, dec2, inp) -# This test bench is a bit different than is usual. Initially when I -# was writing it, I had all of the tests call a function to create a -# device under test and simulator, initialize the dut, run the -# simulation for ~2 cycles, and assert that the dut output what it -# should have. However, this was really slow, since it needed to -# create and tear down the dut and simulator for every test case. - -# Now, instead of doing that, every test case in ALUTestCase puts some -# data into the test_data list below, describing the instructions to -# be tested and the initial state. Once all the tests have been run, -# test_data gets passed to TestRunner which then sets up the DUT and -# simulator once, runs all the data through it, and asserts that the -# results match the pseudocode sim at every cycle. - -# By doing this, I've reduced the time it takes to run the test suite -# massively. Before, it took around 1 minute on my computer, now it -# takes around 3 seconds - - -class LogicalTestCase(FHDLTestCase): - test_data = [] - - def __init__(self, name): - super().__init__(name) - self.test_name = name - - def run_tst_program(self, prog, initial_regs=None, initial_sprs=None): - tc = TestCase(prog, self.test_name, initial_regs, initial_sprs) - self.test_data.append(tc) - - def test_rand(self): - insns = ["and", "or", "xor"] - for i in range(40): - choice = random.choice(insns) - lst = [f"{choice} 3, 1, 2"] - initial_regs = [0] * 32 - initial_regs[1] = random.randint(0, (1 << 64)-1) - initial_regs[2] = random.randint(0, (1 << 64)-1) - self.run_tst_program(Program(lst, bigendian), initial_regs) - - def test_rand_imm_logical(self): - insns = ["andi.", "andis.", "ori", "oris", "xori", "xoris"] - for i in range(10): - choice = random.choice(insns) - imm = random.randint(0, (1 << 16)-1) - lst = [f"{choice} 3, 1, {imm}"] - print(lst) - initial_regs = [0] * 32 - initial_regs[1] = random.randint(0, (1 << 64)-1) - self.run_tst_program(Program(lst, bigendian), initial_regs) - - def test_cntz(self): - insns = ["cntlzd", "cnttzd", "cntlzw", "cnttzw"] - for i in range(100): - choice = random.choice(insns) - lst = [f"{choice} 3, 1"] - print(lst) - initial_regs = [0] * 32 - initial_regs[1] = random.randint(0, (1 << 64)-1) - self.run_tst_program(Program(lst, bigendian), initial_regs) - - def test_parity(self): - insns = ["prtyw", "prtyd"] - for i in range(10): - choice = random.choice(insns) - lst = [f"{choice} 3, 1"] - print(lst) - initial_regs = [0] * 32 - initial_regs[1] = random.randint(0, (1 << 64)-1) - self.run_tst_program(Program(lst, bigendian), initial_regs) - - def test_popcnt(self): - insns = ["popcntb", "popcntw", "popcntd"] - for i in range(10): - choice = random.choice(insns) - lst = [f"{choice} 3, 1"] - print(lst) - initial_regs = [0] * 32 - initial_regs[1] = random.randint(0, (1 << 64)-1) - self.run_tst_program(Program(lst, bigendian), initial_regs) - - def test_popcnt_edge(self): - insns = ["popcntb", "popcntw", "popcntd"] - for choice in insns: - lst = [f"{choice} 3, 1"] - initial_regs = [0] * 32 - initial_regs[1] = -1 - self.run_tst_program(Program(lst, bigendian), initial_regs) - - def test_cmpb(self): - lst = ["cmpb 3, 1, 2"] - initial_regs = [0] * 32 - initial_regs[1] = 0xdeadbeefcafec0de - initial_regs[2] = 0xd0adb0000afec1de - self.run_tst_program(Program(lst, bigendian), initial_regs) - - def test_bpermd(self): - lst = ["bpermd 3, 1, 2"] - for i in range(20): - initial_regs = [0] * 32 - initial_regs[1] = 1 << random.randint(0, 63) - initial_regs[2] = 0xdeadbeefcafec0de - self.run_tst_program(Program(lst, bigendian), initial_regs) - - def test_ilang(self): - pspec = LogicalPipeSpec(id_wid=2) +class LogicalIlangCase(TestAccumulatorBase): + + def case_ilang(self): + class PPspec: + XLEN = 64 + pps = PPspec() + pspec = LogicalPipeSpec(id_wid=2, parent_pspec=pps) alu = LogicalBasePipe(pspec) vl = rtlil.convert(alu, ports=alu.ports()) with open("logical_pipeline.il", "w") as f: f.write(vl) -class TestRunner(FHDLTestCase): - def __init__(self, test_data): - super().__init__("run_all") - self.test_data = test_data - - def run_all(self): +class TestRunner(unittest.TestCase): + + def execute(self, alu, instruction, pdecode2, test): + print(test.name) + program = test.program + self.subTest(test.name) + simulator = ISA(pdecode2, test.regs, test.sprs, test.cr, + test.mem, test.msr, + bigendian=bigendian) + gen = program.generate_instructions() + instructions = list(zip(gen, program.assembly.splitlines())) + + index = simulator.pc.CIA.value//4 + while index < len(instructions): + ins, code = instructions[index] + + print("0x{:X}".format(ins & 0xffffffff)) + print(code) + + # ask the decoder to decode this binary data (endian'd) + yield pdecode2.dec.bigendian.eq(bigendian) # little / big? + yield instruction.eq(ins) # raw binary instr. + yield Settle() + fn_unit = yield pdecode2.e.do.fn_unit + self.assertEqual(fn_unit, Function.LOGICAL.value, code) + yield from set_alu_inputs(alu, pdecode2, simulator) + + # set valid for one cycle, propagate through pipeline... + yield alu.p.i_valid.eq(1) + yield + yield alu.p.i_valid.eq(0) + + opname = code.split(' ')[0] + yield from simulator.call(opname) + index = simulator.pc.CIA.value//4 + + vld = yield alu.n.o_valid + while not vld: + yield + vld = yield alu.n.o_valid + yield + + yield from self.check_alu_outputs(alu, pdecode2, + simulator, code) + yield Settle() + + def test_it(self): + test_data = LogicalIlangCase().test_data + \ + LogicalTestCase().test_data m = Module() comb = m.d.comb instruction = Signal(32) @@ -166,55 +118,25 @@ class TestRunner(FHDLTestCase): m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode) - pspec = LogicalPipeSpec(id_wid=2) + class PPspec: + XLEN = 64 + pps = PPspec() + pspec = LogicalPipeSpec(id_wid=2, parent_pspec=pps) m.submodules.alu = alu = LogicalBasePipe(pspec) - comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.e) - comb += alu.p.valid_i.eq(1) - comb += alu.n.ready_i.eq(1) + comb += alu.p.i_data.ctx.op.eq_from_execute1(pdecode2.do) + comb += alu.n.i_ready.eq(1) comb += pdecode2.dec.raw_opcode_in.eq(instruction) sim = Simulator(m) sim.add_clock(1e-6) def process(): - for test in self.test_data: + for test in test_data: print(test.name) program = test.program - self.subTest(test.name) - simulator = ISA(pdecode2, test.regs, test.sprs, test.cr, - test.mem, test.msr, - bigendian=bigendian) - gen = program.generate_instructions() - instructions = list(zip(gen, program.assembly.splitlines())) - - index = simulator.pc.CIA.value//4 - while index < len(instructions): - ins, code = instructions[index] - - print("0x{:X}".format(ins & 0xffffffff)) - print(code) - - # ask the decoder to decode this binary data (endian'd) - yield pdecode2.dec.bigendian.eq(bigendian) # little / big? - yield instruction.eq(ins) # raw binary instr. - yield Settle() - fn_unit = yield pdecode2.e.do.fn_unit - self.assertEqual(fn_unit, Function.LOGICAL.value, code) - yield from set_alu_inputs(alu, pdecode2, simulator) - yield - opname = code.split(' ')[0] - yield from simulator.call(opname) - index = simulator.pc.CIA.value//4 - - vld = yield alu.n.valid_o - while not vld: - yield - vld = yield alu.n.valid_o - yield - - yield from self.check_alu_outputs(alu, pdecode2, - simulator, code) + with self.subTest(test.name): + yield from self.execute(alu, instruction, pdecode2, test) sim.add_sync_process(process) with sim.write_vcd("logical_simulator.vcd", "logical_simulator.gtkw", @@ -241,13 +163,9 @@ class TestRunner(FHDLTestCase): yield from ALUHelpers.get_wr_sim_cr_a(sim_o, sim, dec2) ALUHelpers.check_cr_a(self, res, sim_o, "CR%d %s" % (cridx, code)) + ALUHelpers.check_xer_ca(self, res, sim_o, code) ALUHelpers.check_int_o(self, res, sim_o, code) if __name__ == "__main__": - unittest.main(exit=False) - suite = unittest.TestSuite() - suite.addTest(TestRunner(LogicalTestCase.test_data)) - - runner = unittest.TextTestRunner() - runner.run(suite) + unittest.main()