X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fsoc%2Ffu%2Flogical%2Ftest%2Ftest_pipe_caller.py;h=a676e8f6020b829d72ae3a28f4e347366ef1a1b0;hb=d6af7e5456b17bab0f542738b17c73d1e66e9160;hp=6223a3dd1886a86bb851f2b71628bd1607858722;hpb=2dccddd26991ba90c60b16f8a8f0f6eff331713a;p=soc.git diff --git a/src/soc/fu/logical/test/test_pipe_caller.py b/src/soc/fu/logical/test/test_pipe_caller.py index 6223a3dd..a676e8f6 100644 --- a/src/soc/fu/logical/test/test_pipe_caller.py +++ b/src/soc/fu/logical/test/test_pipe_caller.py @@ -11,10 +11,8 @@ from soc.decoder.selectable_int import SelectableInt from soc.simulator.program import Program from soc.decoder.isa.all import ISA - from soc.fu.logical.pipeline import LogicalBasePipe -from soc.fu.alu.alu_input_record import CompALUOpSubset -from soc.fu.alu.pipe_data import ALUPipeSpec +from soc.fu.logical.pipe_data import LogicalPipeSpec import random @@ -25,6 +23,7 @@ class TestCase: self.sprs = sprs self.name = name + def get_rec_width(rec): recwidth = 0 # Setup random inputs for dut.op @@ -33,6 +32,7 @@ def get_rec_width(rec): recwidth += width return recwidth + def set_alu_inputs(alu, dec2, sim): # TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43 # detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok)) @@ -65,13 +65,14 @@ def set_alu_inputs(alu, dec2, sim): yield alu.p.data_i.b.eq(data2) - def set_extra_alu_inputs(alu, dec2, sim): carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0 - yield alu.p.data_i.carry_in.eq(carry) + carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0 + yield alu.p.data_i.xer_ca[0].eq(carry) + yield alu.p.data_i.xer_ca[1].eq(carry32) so = 1 if sim.spr['XER'][XER_bits['SO']] else 0 - yield alu.p.data_i.so.eq(so) - + yield alu.p.data_i.xer_so.eq(so) + # This test bench is a bit different than is usual. Initially when I # was writing it, I had all of the tests call a function to create a @@ -98,6 +99,7 @@ class LogicalTestCase(FHDLTestCase): def __init__(self, name): super().__init__(name) self.test_name = name + def run_tst_program(self, prog, initial_regs=[0] * 32, initial_sprs={}): tc = TestCase(prog, initial_regs, initial_sprs, self.test_name) test_data.append(tc) @@ -108,19 +110,19 @@ class LogicalTestCase(FHDLTestCase): choice = random.choice(insns) lst = [f"{choice} 3, 1, 2"] initial_regs = [0] * 32 - initial_regs[1] = random.randint(0, (1<<64)-1) - initial_regs[2] = random.randint(0, (1<<64)-1) + initial_regs[1] = random.randint(0, (1 << 64)-1) + initial_regs[2] = random.randint(0, (1 << 64)-1) self.run_tst_program(Program(lst), initial_regs) def test_rand_imm_logical(self): insns = ["andi.", "andis.", "ori", "oris", "xori", "xoris"] for i in range(10): choice = random.choice(insns) - imm = random.randint(0, (1<<16)-1) + imm = random.randint(0, (1 << 16)-1) lst = [f"{choice} 3, 1, {imm}"] print(lst) initial_regs = [0] * 32 - initial_regs[1] = random.randint(0, (1<<64)-1) + initial_regs[1] = random.randint(0, (1 << 64)-1) self.run_tst_program(Program(lst), initial_regs) def test_cntz(self): @@ -130,7 +132,7 @@ class LogicalTestCase(FHDLTestCase): lst = [f"{choice} 3, 1"] print(lst) initial_regs = [0] * 32 - initial_regs[1] = random.randint(0, (1<<64)-1) + initial_regs[1] = random.randint(0, (1 << 64)-1) self.run_tst_program(Program(lst), initial_regs) def test_parity(self): @@ -140,7 +142,7 @@ class LogicalTestCase(FHDLTestCase): lst = [f"{choice} 3, 1"] print(lst) initial_regs = [0] * 32 - initial_regs[1] = random.randint(0, (1<<64)-1) + initial_regs[1] = random.randint(0, (1 << 64)-1) self.run_tst_program(Program(lst), initial_regs) def test_popcnt(self): @@ -150,7 +152,15 @@ class LogicalTestCase(FHDLTestCase): lst = [f"{choice} 3, 1"] print(lst) initial_regs = [0] * 32 - initial_regs[1] = random.randint(0, (1<<64)-1) + initial_regs[1] = random.randint(0, (1 << 64)-1) + self.run_tst_program(Program(lst), initial_regs) + + def test_popcnt_edge(self): + insns = ["popcntb", "popcntw", "popcntd"] + for choice in insns: + lst = [f"{choice} 3, 1"] + initial_regs = [0] * 32 + initial_regs[1] = -1 self.run_tst_program(Program(lst), initial_regs) def test_cmpb(self): @@ -160,10 +170,18 @@ class LogicalTestCase(FHDLTestCase): initial_regs[2] = 0xd0adb0000afec1de self.run_tst_program(Program(lst), initial_regs) + def test_bpermd(self): + lst = ["bpermd 3, 1, 2"] + for i in range(20): + initial_regs = [0] * 32 + initial_regs[1] = 1<