X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fsoc%2Ffu%2Flogical%2Ftest%2Ftest_pipe_caller.py;h=cd26976e5f5d3833c878f665d68e628ad1a65046;hb=f490900dda4c561977db2f09a0d38bcf5bd3e336;hp=07ef8150530cc9369de74693004ad75907df4225;hpb=d401a033b3a64e8408436ad5a65e27d0d48e71a0;p=soc.git diff --git a/src/soc/fu/logical/test/test_pipe_caller.py b/src/soc/fu/logical/test/test_pipe_caller.py index 07ef8150..cd26976e 100644 --- a/src/soc/fu/logical/test/test_pipe_caller.py +++ b/src/soc/fu/logical/test/test_pipe_caller.py @@ -1,43 +1,37 @@ from nmigen import Module, Signal -from nmigen.back.pysim import Simulator, Delay, Settle + +# NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell +# Also, check out the cxxsim nmigen branch, and latest yosys from git +from nmutil.sim_tmp_alternative import Simulator, Settle + from nmutil.formaltest import FHDLTestCase from nmigen.cli import rtlil import unittest -from soc.decoder.isa.caller import ISACaller, special_sprs -from soc.decoder.power_decoder import (create_pdecode) -from soc.decoder.power_decoder2 import (PowerDecode2) -from soc.decoder.power_enums import (XER_bits, Function) -from soc.decoder.selectable_int import SelectableInt -from soc.simulator.program import Program -from soc.decoder.isa.all import ISA - -from soc.fu.test.common import TestCase +from openpower.decoder.power_decoder import create_pdecode +from openpower.decoder.power_decoder2 import PowerDecode2 +from openpower.decoder.power_enums import (XER_bits, Function) +from openpower.decoder.isa.all import ISA +from openpower.endian import bigendian + + +from openpower.test.common import TestAccumulatorBase, ALUHelpers from soc.fu.logical.pipeline import LogicalBasePipe from soc.fu.logical.pipe_data import LogicalPipeSpec import random +from openpower.test.logical.logical_cases import LogicalTestCase + def get_cu_inputs(dec2, sim): """naming (res) must conform to LogicalFunctionUnit input regspec """ res = {} - # RA (or RC) - reg1_ok = yield dec2.e.read_reg1.ok - if reg1_ok: - data1 = yield dec2.e.read_reg1.data - res['ra'] = sim.gpr(data1).value - - # RB (or immediate) - reg2_ok = yield dec2.e.read_reg2.ok - #imm_ok = yield dec2.e.imm_data.imm_ok - if reg2_ok: - data2 = yield dec2.e.read_reg2.data - data2 = sim.gpr(data2).value - res['rb'] = data2 - #elif imm_ok: - # data2 = yield dec2.e.imm_data.imm - # res['rb'] = data2 + yield from ALUHelpers.get_sim_int_ra(res, sim, dec2) # RA + yield from ALUHelpers.get_sim_int_rb(res, sim, dec2) # RB + yield from ALUHelpers.get_sim_xer_so(res, sim, dec2) # XER.so + + print("alu get_cu_inputs", res) return res @@ -45,123 +39,18 @@ def get_cu_inputs(dec2, sim): def set_alu_inputs(alu, dec2, sim): # TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43 # detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok)) - # and place it into data_i.b + # and place it into i_data.b inp = yield from get_cu_inputs(dec2, sim) - if 'ra' in inp: - yield alu.p.data_i.a.eq(inp['ra']) - if 'rb' in inp: - yield alu.p.data_i.b.eq(inp['rb']) - imm_ok = yield dec2.e.imm_data.imm_ok - if imm_ok: - data2 = yield dec2.e.imm_data.imm - yield alu.p.data_i.b.eq(data2) - - -# This test bench is a bit different than is usual. Initially when I -# was writing it, I had all of the tests call a function to create a -# device under test and simulator, initialize the dut, run the -# simulation for ~2 cycles, and assert that the dut output what it -# should have. However, this was really slow, since it needed to -# create and tear down the dut and simulator for every test case. - -# Now, instead of doing that, every test case in ALUTestCase puts some -# data into the test_data list below, describing the instructions to -# be tested and the initial state. Once all the tests have been run, -# test_data gets passed to TestRunner which then sets up the DUT and -# simulator once, runs all the data through it, and asserts that the -# results match the pseudocode sim at every cycle. - -# By doing this, I've reduced the time it takes to run the test suite -# massively. Before, it took around 1 minute on my computer, now it -# takes around 3 seconds - - -class LogicalTestCase(FHDLTestCase): - test_data = [] - def __init__(self, name): - super().__init__(name) - self.test_name = name - - def run_tst_program(self, prog, initial_regs=None, initial_sprs=None): - tc = TestCase(prog, self.test_name, initial_regs, initial_sprs) - self.test_data.append(tc) - - def test_rand(self): - insns = ["and", "or", "xor"] - for i in range(40): - choice = random.choice(insns) - lst = [f"{choice} 3, 1, 2"] - initial_regs = [0] * 32 - initial_regs[1] = random.randint(0, (1 << 64)-1) - initial_regs[2] = random.randint(0, (1 << 64)-1) - self.run_tst_program(Program(lst), initial_regs) - - def test_rand_imm_logical(self): - insns = ["andi.", "andis.", "ori", "oris", "xori", "xoris"] - for i in range(10): - choice = random.choice(insns) - imm = random.randint(0, (1 << 16)-1) - lst = [f"{choice} 3, 1, {imm}"] - print(lst) - initial_regs = [0] * 32 - initial_regs[1] = random.randint(0, (1 << 64)-1) - self.run_tst_program(Program(lst), initial_regs) - - def test_cntz(self): - insns = ["cntlzd", "cnttzd", "cntlzw", "cnttzw"] - for i in range(100): - choice = random.choice(insns) - lst = [f"{choice} 3, 1"] - print(lst) - initial_regs = [0] * 32 - initial_regs[1] = random.randint(0, (1 << 64)-1) - self.run_tst_program(Program(lst), initial_regs) - - def test_parity(self): - insns = ["prtyw", "prtyd"] - for i in range(10): - choice = random.choice(insns) - lst = [f"{choice} 3, 1"] - print(lst) - initial_regs = [0] * 32 - initial_regs[1] = random.randint(0, (1 << 64)-1) - self.run_tst_program(Program(lst), initial_regs) - - def test_popcnt(self): - insns = ["popcntb", "popcntw", "popcntd"] - for i in range(10): - choice = random.choice(insns) - lst = [f"{choice} 3, 1"] - print(lst) - initial_regs = [0] * 32 - initial_regs[1] = random.randint(0, (1 << 64)-1) - self.run_tst_program(Program(lst), initial_regs) - - def test_popcnt_edge(self): - insns = ["popcntb", "popcntw", "popcntd"] - for choice in insns: - lst = [f"{choice} 3, 1"] - initial_regs = [0] * 32 - initial_regs[1] = -1 - self.run_tst_program(Program(lst), initial_regs) - - def test_cmpb(self): - lst = ["cmpb 3, 1, 2"] - initial_regs = [0] * 32 - initial_regs[1] = 0xdeadbeefcafec0de - initial_regs[2] = 0xd0adb0000afec1de - self.run_tst_program(Program(lst), initial_regs) - - def test_bpermd(self): - lst = ["bpermd 3, 1, 2"] - for i in range(20): - initial_regs = [0] * 32 - initial_regs[1] = 1<