X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fsoc%2Ffu%2Fmmu%2Ffsm.py;h=7be930ccf27093c351bbc8886c14c8db39140724;hb=46e052c8475d4c43792a44802dad3cec7f67ebbc;hp=b3d09b4e7e36bf1b0c7ff09995f15b40ac8a209a;hpb=9e0dd5f9da1dbe0d7a6a84b3cbd03bbaf2239c2e;p=soc.git

diff --git a/src/soc/fu/mmu/fsm.py b/src/soc/fu/mmu/fsm.py
index b3d09b4e..7be930cc 100644
--- a/src/soc/fu/mmu/fsm.py
+++ b/src/soc/fu/mmu/fsm.py
@@ -2,6 +2,7 @@
 Based on microwatt mmu.vhdl
 
 * https://bugs.libre-soc.org/show_bug.cgi?id=491
+* https://bugs.libre-soc.org/show_bug.cgi?id=450
 """
 
 from nmigen import Elaboratable, Module, Signal, Shape, unsigned, Cat, Mux
@@ -41,8 +42,8 @@ class FSMMMUStage(ControlBase):
         self.pspec = pspec
 
         # set up p/n data
-        self.p.data_i = MMUInputData(pspec)
-        self.n.data_o = MMUOutputData(pspec)
+        self.p.i_data = MMUInputData(pspec)
+        self.n.o_data = MMUOutputData(pspec)
 
         self.mmu = MMU()
 
@@ -51,7 +52,7 @@ class FSMMMUStage(ControlBase):
         self.illegal = Signal()
 
         # for SPR field number access
-        i = self.p.data_i
+        i = self.p.i_data
         self.fields = DecodeFields(SignalBitRange, [i.ctx.op.insn])
         self.fields.create_specs()
 
@@ -68,7 +69,7 @@ class FSMMMUStage(ControlBase):
     def elaborate(self, platform):
         assert hasattr(self, "dcache"), "remember to call set_ldst_interface"
         m = super().elaborate(platform)
-        comb = m.d.comb
+        comb, sync = m.d.comb, m.d.sync
         dcache = self.dcache
 
         # link mmu and dcache together
@@ -82,14 +83,14 @@ class FSMMMUStage(ControlBase):
         wb_out, wb_in = dcache.wb_out, dcache.wb_in
 
         # link ldst and MMU together
-        comb += l_in.eq(ldst.l_in)
-        comb += ldst.l_out.eq(l_out)
+        comb += l_in.eq(ldst.m_out)
+        comb += ldst.m_in.eq(l_out)
 
-        data_i, data_o = self.p.data_i, self.n.data_o
-        a_i, b_i, o, spr1_o = data_i.ra, data_i.rb, data_o.o, data_o.spr1
-        op = data_i.ctx.op
+        i_data, o_data = self.p.i_data, self.n.o_data
+        a_i, b_i, o, spr1_o = i_data.ra, i_data.rb, o_data.o, o_data.spr1
+        op = i_data.ctx.op
         msr_i = op.msr
-        spr1_i = data_i.spr1
+        spr1_i = i_data.spr1
 
         # these are set / got here *ON BEHALF* of LoadStore1
         dsisr, dar = ldst.dsisr, ldst.dar
@@ -118,7 +119,7 @@ class FSMMMUStage(ControlBase):
 
         with m.If(~busy):
             with m.If(self.p.valid_i):
-                m.d.sync += busy.eq(1)
+                sync += busy.eq(1)
         with m.Else():
 
             # based on the Micro-Op, we work out which of MMU or DCache
@@ -144,10 +145,11 @@ class FSMMMUStage(ControlBase):
                     with m.If(~spr[9] & ~spr[5]):
                         comb += self.debug0.eq(3)
                         #if matched update local cached value
-                        with m.If(spr[0]):
-                            m.d.sync += dsisr.eq(a_i[:32])
-                        with m.Else():
-                            m.d.sync += dar.eq(a_i)
+                        #commented out because there is a driver conflict
+                        #with m.If(spr[0]):
+                        #    sync += dsisr.eq(a_i[:32])
+                        #with m.Else():
+                        #    sync += dar.eq(a_i)
                         comb += done.eq(1)
                     # pass it over to the MMU instead
                     with m.Else():
@@ -216,7 +218,7 @@ class FSMMMUStage(ControlBase):
                     comb += self.illegal.eq(1)
 
             with m.If(self.n.ready_i & self.n.valid_o):
-                m.d.sync += busy.eq(0)
+                sync += busy.eq(0)
 
         return m