X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fsoc%2Ffu%2Fmul%2Fmul_input_record.py;h=6e1683711637fe6a3d83574a0a8d54c54b410803;hb=65c43ae4c522d129742046eb2e1395ce27d48a09;hp=8554c5361e117544d04a817aef7f5206fca21156;hpb=61e77b4066b26373b7bbb369f23b07a5705d4141;p=soc.git diff --git a/src/soc/fu/mul/mul_input_record.py b/src/soc/fu/mul/mul_input_record.py index 8554c536..6e168371 100644 --- a/src/soc/fu/mul/mul_input_record.py +++ b/src/soc/fu/mul/mul_input_record.py @@ -1,9 +1,10 @@ -from nmigen.hdl.rec import Record, Layout +from soc.fu.base_input_record import CompOpSubsetBase +from nmigen.hdl.rec import Layout -from soc.decoder.power_enums import InternalOp, Function, CryIn +from soc.decoder.power_enums import MicrOp, Function, CryIn -class CompMULOpSubset(Record): +class CompMULOpSubset(CompOpSubsetBase): """CompMULOpSubset a copy of the relevant subset information from Decode2Execute1Type @@ -11,50 +12,19 @@ class CompMULOpSubset(Record): grab subsets. """ def __init__(self, name=None): - layout = (('insn_type', InternalOp), + layout = (('insn_type', MicrOp), ('fn_unit', Function), ('imm_data', Layout((("imm", 64), ("imm_ok", 1)))), ('rc', Layout((("rc", 1), ("rc_ok", 1)))), # Data ('oe', Layout((("oe", 1), ("oe_ok", 1)))), # Data - ('invert_a', 1), + ('invert_in', 1), ('zero_a', 1), ('invert_out', 1), ('write_cr0', 1), - ('input_carry', CryIn), - ('output_carry', 1), ('is_32bit', 1), ('is_signed', 1), ('insn', 32), ) - Record.__init__(self, Layout(layout), name=name) + super().__init__(layout, name=name) - # grrr. Record does not have kwargs - self.insn_type.reset_less = True - self.fn_unit.reset_less = True - self.zero_a.reset_less = True - self.invert_a.reset_less = True - self.invert_out.reset_less = True - self.input_carry.reset_less = True - self.output_carry.reset_less = True - self.is_32bit.reset_less = True - self.is_signed.reset_less = True - - def eq_from_execute1(self, other): - """ use this to copy in from Decode2Execute1Type - """ - res = [] - for fname, sig in self.fields.items(): - eqfrom = other.do.fields[fname] - res.append(sig.eq(eqfrom)) - return res - - def ports(self): - return [self.insn_type, - self.invert_a, - self.invert_out, - self.input_carry, - self.output_carry, - self.is_32bit, - self.is_signed, - ]