X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fsoc%2Ffu%2Fshift_rot%2Ftest%2Ftest_pipe_caller.py;h=00bb3262e9db799cca55383aa0c181e598a400b5;hb=20ffa8ec223be44fc37df5184ca09d648e85a844;hp=f73f9b2374e68730d2041a54202448dbaaedde16;hpb=736b7c87a60181ba6c761ddcf1b70487bcb80e41;p=soc.git diff --git a/src/soc/fu/shift_rot/test/test_pipe_caller.py b/src/soc/fu/shift_rot/test/test_pipe_caller.py index f73f9b23..00bb3262 100644 --- a/src/soc/fu/shift_rot/test/test_pipe_caller.py +++ b/src/soc/fu/shift_rot/test/test_pipe_caller.py @@ -1,28 +1,22 @@ -from nmigen import Module, Signal -from nmigen.back.pysim import Simulator, Delay, Settle -from nmutil.formaltest import FHDLTestCase -from nmigen.cli import rtlil +import random +from soc.fu.shift_rot.pipe_data import ShiftRotPipeSpec +from soc.fu.shift_rot.pipeline import ShiftRotBasePipe +from openpower.test.common import TestAccumulatorBase, TestCase, ALUHelpers +from openpower.endian import bigendian +from openpower.decoder.isa.all import ISA +from openpower.simulator.program import Program +from openpower.decoder.power_enums import (XER_bits, Function, CryIn) +from openpower.decoder.power_decoder2 import (PowerDecode2) +from openpower.decoder.power_decoder import (create_pdecode) import unittest -from soc.decoder.isa.caller import ISACaller, special_sprs -from soc.decoder.power_decoder import (create_pdecode) -from soc.decoder.power_decoder2 import (PowerDecode2) -from soc.decoder.power_enums import (XER_bits, Function, CryIn) -from soc.decoder.selectable_int import SelectableInt -from soc.simulator.program import Program -from soc.decoder.isa.all import ISA - +from nmigen.cli import rtlil +from nmigen import Module, Signal -from soc.fu.shift_rot.pipeline import ShiftRotBasePipe -from soc.fu.alu.alu_input_record import CompALUOpSubset -from soc.fu.shift_rot.pipe_data import ShiftRotPipeSpec -import random +# NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell +# Also, check out the cxxsim nmigen branch, and latest yosys from git +from nmutil.sim_tmp_alternative import Simulator, Settle -class TestCase: - def __init__(self, program, regs, sprs, name): - self.program = program - self.regs = regs - self.sprs = sprs - self.name = name +from openpower.test.shift_rot.shift_rot_cases import ShiftRotTestCase def get_cu_inputs(dec2, sim): @@ -30,32 +24,13 @@ def get_cu_inputs(dec2, sim): """ res = {} - # RA - reg1_ok = yield dec2.e.read_reg1.ok - if reg1_ok: - data1 = yield dec2.e.read_reg1.data - res['ra'] = sim.gpr(data1).value - - # RB - reg2_ok = yield dec2.e.read_reg2.ok - if reg2_ok: - data2 = yield dec2.e.read_reg2.data - res['rb'] = sim.gpr(data2).value - - # RS (RC) - reg3_ok = yield dec2.e.read_reg3.ok - if reg3_ok: - data3 = yield dec2.e.read_reg3.data - res['rc'] = sim.gpr(data3).value - - # XER.ca - cry_in = yield dec2.e.input_carry - if cry_in == CryIn.CA.value: - carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0 - carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0 - res['xer_ca'] = carry | (carry32<<1) - - print ("inputs", res) + yield from ALUHelpers.get_sim_int_ra(res, sim, dec2) # RA + yield from ALUHelpers.get_sim_int_rb(res, sim, dec2) # RB + yield from ALUHelpers.get_sim_int_rc(res, sim, dec2) # RC + yield from ALUHelpers.get_rd_sim_xer_ca(res, sim, dec2) # XER.ca + yield from ALUHelpers.get_sim_xer_so(res, sim, dec2) # XER.so + + print("alu get_cu_inputs", res) return res @@ -63,34 +38,15 @@ def get_cu_inputs(dec2, sim): def set_alu_inputs(alu, dec2, sim): # TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43 # detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok)) - # and place it into data_i.b + # and place it into i_data.b inp = yield from get_cu_inputs(dec2, sim) - if 'ra' in inp: - yield alu.p.data_i.a.eq(inp['ra']) - else: - yield alu.p.data_i.a.eq(0) - if 'rb' in inp: - yield alu.p.data_i.rb.eq(inp['rb']) - else: - yield alu.p.data_i.rb.eq(0) - if 'rc' in inp: - yield alu.p.data_i.rs.eq(inp['rc']) - else: - yield alu.p.data_i.rs.eq(0) - - # If there's an immediate, set the B operand to that - imm_ok = yield dec2.e.imm_data.imm_ok - if imm_ok: - data2 = yield dec2.e.imm_data.imm - yield alu.p.data_i.rb.eq(data2) - - if 'xer_ca' in inp: - yield alu.p.data_i.xer_ca.eq(inp['xer_ca']) - print ("extra inputs: CA/32", bin(inp['xer_ca'])) - else: - yield alu.p.data_i.xer_ca.eq(0) - + yield from ALUHelpers.set_int_ra(alu, dec2, inp) + yield from ALUHelpers.set_int_rb(alu, dec2, inp) + yield from ALUHelpers.set_int_rc(alu, dec2, inp) + yield from ALUHelpers.set_xer_ca(alu, dec2, inp) + yield from ALUHelpers.set_xer_so(alu, dec2, inp) + # This test bench is a bit different than is usual. Initially when I # was writing it, I had all of the tests call a function to create a @@ -110,189 +66,134 @@ def set_alu_inputs(alu, dec2, sim): # massively. Before, it took around 1 minute on my computer, now it # takes around 3 seconds -test_data = [] - - -class ShiftRotTestCase(FHDLTestCase): - def __init__(self, name): - super().__init__(name) - self.test_name = name - def run_tst_program(self, prog, initial_regs=[0] * 32, initial_sprs={}): - tc = TestCase(prog, initial_regs, initial_sprs, self.test_name) - test_data.append(tc) - - - def test_shift(self): - insns = ["slw", "sld", "srw", "srd", "sraw", "srad"] - for i in range(20): - choice = random.choice(insns) - lst = [f"{choice} 3, 1, 2"] - initial_regs = [0] * 32 - initial_regs[1] = random.randint(0, (1<<64)-1) - initial_regs[2] = random.randint(0, 63) - print(initial_regs[1], initial_regs[2]) - self.run_tst_program(Program(lst), initial_regs) - - - def test_shift_arith(self): - lst = ["sraw 3, 1, 2"] - initial_regs = [0] * 32 - initial_regs[1] = random.randint(0, (1<<64)-1) - initial_regs[2] = random.randint(0, 63) - print(initial_regs[1], initial_regs[2]) - self.run_tst_program(Program(lst), initial_regs) - - def test_shift_once(self): - lst = ["slw 3, 1, 4", - "slw 3, 1, 2"] - initial_regs = [0] * 32 - initial_regs[1] = 0x80000000 - initial_regs[2] = 0x40 - initial_regs[4] = 0x00 - self.run_tst_program(Program(lst), initial_regs) - - def test_rlwinm(self): - for i in range(10): - mb = random.randint(0,31) - me = random.randint(0,31) - sh = random.randint(0,31) - lst = [f"rlwinm 3, 1, {mb}, {me}, {sh}", - #f"rlwinm. 3, 1, {mb}, {me}, {sh}" - ] - initial_regs = [0] * 32 - initial_regs[1] = random.randint(0, (1<<64)-1) - self.run_tst_program(Program(lst), initial_regs) - - def test_rlwimi(self): - lst = ["rlwimi 3, 1, 5, 20, 6"] - initial_regs = [0] * 32 - initial_regs[1] = 0xdeadbeef - initial_regs[3] = 0x12345678 - self.run_tst_program(Program(lst), initial_regs) - - def test_rlwnm(self): - lst = ["rlwnm 3, 1, 2, 20, 6"] - initial_regs = [0] * 32 - initial_regs[1] = random.randint(0, (1<<64)-1) - initial_regs[2] = random.randint(0, 63) - self.run_tst_program(Program(lst), initial_regs) - - def test_rldicl(self): - lst = ["rldicl 3, 1, 5, 20"] - initial_regs = [0] * 32 - initial_regs[1] = random.randint(0, (1<<64)-1) - self.run_tst_program(Program(lst), initial_regs) - - def test_rldicr(self): - lst = ["rldicr 3, 1, 5, 20"] - initial_regs = [0] * 32 - initial_regs[1] = random.randint(0, (1<<64)-1) - self.run_tst_program(Program(lst), initial_regs) - - def test_rlc(self): - insns = ["rldic", "rldicl", "rldicr"] - for i in range(20): - choice = random.choice(insns) - sh = random.randint(0, 63) - m = random.randint(0, 63) - lst = [f"{choice} 3, 1, {sh}, {m}"] - initial_regs = [0] * 32 - initial_regs[1] = random.randint(0, (1<<64)-1) - self.run_tst_program(Program(lst), initial_regs) - - def test_ilang(self): + +class ShiftRotIlangCase(TestAccumulatorBase): + + def case_ilang(self): pspec = ShiftRotPipeSpec(id_wid=2) + pspec.draft_bitmanip = True alu = ShiftRotBasePipe(pspec) vl = rtlil.convert(alu, ports=alu.ports()) - with open("pipeline.il", "w") as f: + with open("shift_rot_pipeline.il", "w") as f: f.write(vl) -class TestRunner(FHDLTestCase): +class TestRunner(unittest.TestCase): def __init__(self, test_data): super().__init__("run_all") self.test_data = test_data + def execute(self, alu, instruction, pdecode2, test): + program = test.program + simulator = ISA(pdecode2, test.regs, test.sprs, test.cr, + test.mem, test.msr, + bigendian=bigendian) + gen = program.generate_instructions() + instructions = list(zip(gen, program.assembly.splitlines())) + + index = simulator.pc.CIA.value//4 + while index < len(instructions): + ins, code = instructions[index] + + print("0x{:X}".format(ins & 0xffffffff)) + print(code) + + # ask the decoder to decode this binary data (endian'd) + yield pdecode2.dec.bigendian.eq(bigendian) # little / big? + yield instruction.eq(ins) # raw binary instr. + yield Settle() + fn_unit = yield pdecode2.e.do.fn_unit + self.assertEqual(fn_unit, Function.SHIFT_ROT.value) + yield from set_alu_inputs(alu, pdecode2, simulator) + + # set valid for one cycle, propagate through pipeline... + yield alu.p.i_valid.eq(1) + yield + yield alu.p.i_valid.eq(0) + + opname = code.split(' ')[0] + yield from simulator.call(opname) + index = simulator.pc.CIA.value//4 + + vld = yield alu.n.o_valid + while not vld: + yield + vld = yield alu.n.o_valid + yield + alu_out = yield alu.n.o_data.o.data + + yield from self.check_alu_outputs(alu, pdecode2, + simulator, code) + yield Settle() + def run_all(self): m = Module() comb = m.d.comb instruction = Signal(32) - pdecode = create_pdecode() + fn_name = "SHIFT_ROT" + opkls = ShiftRotPipeSpec.opsubsetkls - m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode) + m.submodules.pdecode2 = pdecode2 = PowerDecode2(None, opkls, fn_name) + pdecode = pdecode2.dec pspec = ShiftRotPipeSpec(id_wid=2) + pspec.draft_bitmanip = True m.submodules.alu = alu = ShiftRotBasePipe(pspec) - comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.e) - comb += alu.p.valid_i.eq(1) - comb += alu.n.ready_i.eq(1) + comb += alu.p.i_data.ctx.op.eq_from_execute1(pdecode2.do) + comb += alu.n.i_ready.eq(1) comb += pdecode2.dec.raw_opcode_in.eq(instruction) sim = Simulator(m) sim.add_clock(1e-6) + def process(): for test in self.test_data: print(test.name) program = test.program - self.subTest(test.name) - simulator = ISA(pdecode2, test.regs, test.sprs, 0) - gen = program.generate_instructions() - instructions = list(zip(gen, program.assembly.splitlines())) - - index = simulator.pc.CIA.value//4 - while index < len(instructions): - ins, code = instructions[index] - - print("0x{:X}".format(ins & 0xffffffff)) - print(code) - - # ask the decoder to decode this binary data (endian'd) - yield pdecode2.dec.bigendian.eq(0) # little / big? - yield instruction.eq(ins) # raw binary instr. - yield Settle() - fn_unit = yield pdecode2.e.fn_unit - self.assertEqual(fn_unit, Function.SHIFT_ROT.value) - yield from set_alu_inputs(alu, pdecode2, simulator) - yield - opname = code.split(' ')[0] - yield from simulator.call(opname) - index = simulator.pc.CIA.value//4 - - vld = yield alu.n.valid_o - while not vld: - yield - vld = yield alu.n.valid_o - yield - alu_out = yield alu.n.data_o.o.data - out_reg_valid = yield pdecode2.e.write_reg.ok - if out_reg_valid: - write_reg_idx = yield pdecode2.e.write_reg.data - expected = simulator.gpr(write_reg_idx).value - msg = f"expected {expected:x}, actual: {alu_out:x}" - self.assertEqual(expected, alu_out, msg) - yield from self.check_extra_alu_outputs(alu, pdecode2, - simulator) - break + with self.subTest(test.name): + yield from self.execute(alu, instruction, pdecode2, test) sim.add_sync_process(process) - with sim.write_vcd("simulator.vcd", "simulator.gtkw", - traces=[]): + with sim.write_vcd("shift_rot_simulator.vcd"): sim.run() - def check_extra_alu_outputs(self, alu, dec2, sim): - rc = yield dec2.e.rc.data + def check_alu_outputs(self, alu, dec2, sim, code): + + rc = yield dec2.e.do.rc.rc + cridx_ok = yield dec2.e.write_cr.ok + cridx = yield dec2.e.write_cr.data + + print("check extra output", repr(code), cridx_ok, cridx) if rc: - cr_expected = sim.crl[0].get_range().value - cr_actual = yield alu.n.data_o.cr0 - self.assertEqual(cr_expected, cr_actual) + self.assertEqual(cridx, 0, code) + + sim_o = {} + res = {} + + yield from ALUHelpers.get_cr_a(res, alu, dec2) + yield from ALUHelpers.get_xer_ca(res, alu, dec2) + yield from ALUHelpers.get_int_o(res, alu, dec2) + + print("hw outputs", res) + + yield from ALUHelpers.get_sim_int_o(sim_o, sim, dec2) + yield from ALUHelpers.get_wr_sim_cr_a(sim_o, sim, dec2) + yield from ALUHelpers.get_wr_sim_xer_ca(sim_o, sim, dec2) + + print("sim outputs", sim_o) + + ALUHelpers.check_cr_a(self, res, sim_o, "CR%d %s" % (cridx, code)) + ALUHelpers.check_xer_ca(self, res, sim_o, code) + ALUHelpers.check_int_o(self, res, sim_o, code) if __name__ == "__main__": unittest.main(exit=False) suite = unittest.TestSuite() - suite.addTest(TestRunner(test_data)) + suite.addTest(TestRunner(ShiftRotTestCase().test_data)) + suite.addTest(TestRunner(ShiftRotIlangCase().test_data)) runner = unittest.TextTestRunner() runner.run(suite)