X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fsoc%2Ffu%2Fshift_rot%2Ftest%2Ftest_pipe_caller.py;h=a5de04bcfeab4400ab01ae01ebd30937f88bd3be;hb=1d37414e3125754bcf1481657ba7820c03151aa7;hp=fb370525bade385e5e6d7bd9f6049c633d0a6e3e;hpb=c150af84a0c52f5297e55dbcfdaf334f05a6e994;p=soc.git diff --git a/src/soc/fu/shift_rot/test/test_pipe_caller.py b/src/soc/fu/shift_rot/test/test_pipe_caller.py index fb370525..a5de04bc 100644 --- a/src/soc/fu/shift_rot/test/test_pipe_caller.py +++ b/src/soc/fu/shift_rot/test/test_pipe_caller.py @@ -1,71 +1,60 @@ -from nmigen import Module, Signal -from nmigen.back.pysim import Simulator, Delay, Settle -from nmigen.test.utils import FHDLTestCase -from nmigen.cli import rtlil -import unittest -from soc.decoder.isa.caller import ISACaller, special_sprs -from soc.decoder.power_decoder import (create_pdecode) -from soc.decoder.power_decoder2 import (PowerDecode2) -from soc.decoder.power_enums import (XER_bits, Function) -from soc.decoder.selectable_int import SelectableInt -from soc.simulator.program import Program +import random +from soc.fu.shift_rot.pipe_data import ShiftRotPipeSpec +from soc.fu.alu.alu_input_record import CompALUOpSubset +from soc.fu.shift_rot.pipeline import ShiftRotBasePipe +from soc.fu.test.common import TestAccumulatorBase, TestCase, ALUHelpers +from soc.config.endian import bigendian from soc.decoder.isa.all import ISA +from soc.simulator.program import Program +from soc.decoder.selectable_int import SelectableInt +from soc.decoder.power_enums import (XER_bits, Function, CryIn) +from soc.decoder.power_decoder2 import (PowerDecode2) +from soc.decoder.power_decoder import (create_pdecode) +from soc.decoder.isa.caller import ISACaller, special_sprs +import unittest +from nmigen.cli import rtlil +from nmigen import Module, Signal +from nmigen.back.pysim import Delay, Settle +# NOTE: to use this (set to True), at present it is necessary to check +# out the cxxsim nmigen branch +cxxsim = False +if cxxsim: + try: + from nmigen.sim.cxxsim import Simulator + except ImportError: + print("nope, sorry, have to use nmigen cxxsim branch for now") + cxxsim = False + from nmigen.back.pysim import Simulator +else: + from nmigen.back.pysim import Simulator -from soc.fu.shift_rot.pipeline import ShiftRotBasePipe -from soc.fu.alu.alu_input_record import CompALUOpSubset -from soc.fu.shift_rot.pipe_data import ShiftRotPipeSpec -import random +def get_cu_inputs(dec2, sim): + """naming (res) must conform to ShiftRotFunctionUnit input regspec + """ + res = {} -class TestCase: - def __init__(self, program, regs, sprs, name): - self.program = program - self.regs = regs - self.sprs = sprs - self.name = name + yield from ALUHelpers.get_sim_int_ra(res, sim, dec2) # RA + yield from ALUHelpers.get_sim_int_rb(res, sim, dec2) # RB + yield from ALUHelpers.get_sim_int_rc(res, sim, dec2) # RC + yield from ALUHelpers.get_rd_sim_xer_ca(res, sim, dec2) # XER.ca + + print("inputs", res) + + return res def set_alu_inputs(alu, dec2, sim): - inputs = [] # TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43 # detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok)) # and place it into data_i.b - reg3_ok = yield dec2.e.read_reg3.ok - if reg3_ok: - reg3_sel = yield dec2.e.read_reg3.data - data3 = sim.gpr(reg3_sel).value - else: - data3 = 0 - reg1_ok = yield dec2.e.read_reg1.ok - if reg1_ok: - reg1_sel = yield dec2.e.read_reg1.data - data1 = sim.gpr(reg1_sel).value - else: - data1 = 0 - reg2_ok = yield dec2.e.read_reg2.ok - imm_ok = yield dec2.e.imm_data.ok - if reg2_ok: - reg2_sel = yield dec2.e.read_reg2.data - data2 = sim.gpr(reg2_sel).value - elif imm_ok: - data2 = yield dec2.e.imm_data.imm - else: - data2 = 0 - - yield alu.p.data_i.a.eq(data1) - yield alu.p.data_i.rb.eq(data2) - yield alu.p.data_i.rs.eq(data3) - - -def set_extra_alu_inputs(alu, dec2, sim): - carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0 - carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0 - yield alu.p.data_i.xer_ca[0].eq(carry) - yield alu.p.data_i.xer_ca[1].eq(carry32) - so = 1 if sim.spr['XER'][XER_bits['SO']] else 0 - yield alu.p.data_i.xer_so.eq(so) - + inp = yield from get_cu_inputs(dec2, sim) + yield from ALUHelpers.set_int_ra(alu, dec2, inp) + yield from ALUHelpers.set_int_rb(alu, dec2, inp) + yield from ALUHelpers.set_int_rc(alu, dec2, inp) + yield from ALUHelpers.set_xer_ca(alu, dec2, inp) + # This test bench is a bit different than is usual. Initially when I # was writing it, I had all of the tests call a function to create a @@ -85,84 +74,114 @@ def set_extra_alu_inputs(alu, dec2, sim): # massively. Before, it took around 1 minute on my computer, now it # takes around 3 seconds -test_data = [] +class ShiftRotTestCase(TestAccumulatorBase): -class ShiftRotTestCase(FHDLTestCase): - def __init__(self, name): - super().__init__(name) - self.test_name = name - def run_tst_program(self, prog, initial_regs=[0] * 32, initial_sprs={}): - tc = TestCase(prog, initial_regs, initial_sprs, self.test_name) - test_data.append(tc) - + def case_0_proof_regression_rlwnm(self): + lst = ["rlwnm 3, 1, 2, 16, 20"] + initial_regs = [0] * 32 + initial_regs[1] = 0x7ffdbffb91b906b9 + initial_regs[2] = 31 + print(initial_regs[1], initial_regs[2]) + self.add_case(Program(lst, bigendian), initial_regs) - def test_shift(self): + def case_shift(self): insns = ["slw", "sld", "srw", "srd", "sraw", "srad"] for i in range(20): choice = random.choice(insns) lst = [f"{choice} 3, 1, 2"] initial_regs = [0] * 32 - initial_regs[1] = random.randint(0, (1<<64)-1) + initial_regs[1] = random.randint(0, (1 << 64)-1) initial_regs[2] = random.randint(0, 63) print(initial_regs[1], initial_regs[2]) - self.run_tst_program(Program(lst), initial_regs) + self.add_case(Program(lst, bigendian), initial_regs) - - def test_shift_arith(self): + def case_shift_arith(self): lst = ["sraw 3, 1, 2"] initial_regs = [0] * 32 - initial_regs[1] = random.randint(0, (1<<64)-1) + initial_regs[1] = random.randint(0, (1 << 64)-1) initial_regs[2] = random.randint(0, 63) print(initial_regs[1], initial_regs[2]) - self.run_tst_program(Program(lst), initial_regs) + self.add_case(Program(lst, bigendian), initial_regs) - def test_shift_once(self): + def case_shift_once(self): lst = ["slw 3, 1, 4", "slw 3, 1, 2"] initial_regs = [0] * 32 initial_regs[1] = 0x80000000 initial_regs[2] = 0x40 initial_regs[4] = 0x00 - self.run_tst_program(Program(lst), initial_regs) + self.add_case(Program(lst, bigendian), initial_regs) - def test_rlwinm(self): + def case_rlwinm(self): for i in range(10): - mb = random.randint(0,31) - me = random.randint(0,31) - sh = random.randint(0,31) - lst = [f"rlwinm 3, 1, {mb}, {me}, {sh}"] + mb = random.randint(0, 31) + me = random.randint(0, 31) + sh = random.randint(0, 31) + lst = [f"rlwinm 3, 1, {mb}, {me}, {sh}", + #f"rlwinm. 3, 1, {mb}, {me}, {sh}" + ] initial_regs = [0] * 32 - initial_regs[1] = random.randint(0, (1<<64)-1) - self.run_tst_program(Program(lst), initial_regs) + initial_regs[1] = random.randint(0, (1 << 64)-1) + self.add_case(Program(lst, bigendian), initial_regs) - def test_rlwimi(self): + def case_rlwimi(self): lst = ["rlwimi 3, 1, 5, 20, 6"] initial_regs = [0] * 32 initial_regs[1] = 0xdeadbeef initial_regs[3] = 0x12345678 - self.run_tst_program(Program(lst), initial_regs) + self.add_case(Program(lst, bigendian), initial_regs) - def test_rlwnm(self): + def case_rlwnm(self): lst = ["rlwnm 3, 1, 2, 20, 6"] initial_regs = [0] * 32 - initial_regs[1] = random.randint(0, (1<<64)-1) + initial_regs[1] = random.randint(0, (1 << 64)-1) initial_regs[2] = random.randint(0, 63) - self.run_tst_program(Program(lst), initial_regs) + self.add_case(Program(lst, bigendian), initial_regs) - def test_rldicl(self): + def case_rldicl(self): lst = ["rldicl 3, 1, 5, 20"] initial_regs = [0] * 32 - initial_regs[1] = random.randint(0, (1<<64)-1) - self.run_tst_program(Program(lst), initial_regs) + initial_regs[1] = random.randint(0, (1 << 64)-1) + self.add_case(Program(lst, bigendian), initial_regs) - def test_rldicr(self): + def case_rldicr(self): lst = ["rldicr 3, 1, 5, 20"] initial_regs = [0] * 32 - initial_regs[1] = random.randint(0, (1<<64)-1) - self.run_tst_program(Program(lst), initial_regs) + initial_regs[1] = random.randint(0, (1 << 64)-1) + self.add_case(Program(lst, bigendian), initial_regs) + + def case_regression_extswsli(self): + lst = [f"extswsli 3, 1, 34"] + initial_regs = [0] * 32 + initial_regs[1] = 0x5678 + self.add_case(Program(lst, bigendian), initial_regs) - def test_rlc(self): + def case_regression_extswsli_2(self): + lst = [f"extswsli 3, 1, 7"] + initial_regs = [0] * 32 + initial_regs[1] = 0x3ffffd7377f19fdd + self.add_case(Program(lst, bigendian), initial_regs) + + def case_regression_extswsli_3(self): + lst = [f"extswsli 3, 1, 0"] + initial_regs = [0] * 32 + #initial_regs[1] = 0x80000000fb4013e2 + #initial_regs[1] = 0xffffffffffffffff + #initial_regs[1] = 0x00000000ffffffff + initial_regs[1] = 0x0000010180122900 + #initial_regs[1] = 0x3ffffd73f7f19fdd + self.add_case(Program(lst, bigendian), initial_regs) + + def case_extswsli(self): + for i in range(40): + sh = random.randint(0, 63) + lst = [f"extswsli 3, 1, {sh}"] + initial_regs = [0] * 32 + initial_regs[1] = random.randint(0, (1 << 64)-1) + self.add_case(Program(lst, bigendian), initial_regs) + + def case_rlc(self): insns = ["rldic", "rldicl", "rldicr"] for i in range(20): choice = random.choice(insns) @@ -170,10 +189,10 @@ class ShiftRotTestCase(FHDLTestCase): m = random.randint(0, 63) lst = [f"{choice} 3, 1, {sh}, {m}"] initial_regs = [0] * 32 - initial_regs[1] = random.randint(0, (1<<64)-1) - self.run_tst_program(Program(lst), initial_regs) + initial_regs[1] = random.randint(0, (1 << 64)-1) + self.add_case(Program(lst, bigendian), initial_regs) - def test_ilang(self): + def case_ilang(self): pspec = ShiftRotPipeSpec(id_wid=2) alu = ShiftRotBasePipe(pspec) vl = rtlil.convert(alu, ports=alu.ports()) @@ -181,11 +200,48 @@ class ShiftRotTestCase(FHDLTestCase): f.write(vl) -class TestRunner(FHDLTestCase): +class TestRunner(unittest.TestCase): def __init__(self, test_data): super().__init__("run_all") self.test_data = test_data + def execute(self, alu, instruction, pdecode2, test): + program = test.program + simulator = ISA(pdecode2, test.regs, test.sprs, test.cr, + test.mem, test.msr, + bigendian=bigendian) + gen = program.generate_instructions() + instructions = list(zip(gen, program.assembly.splitlines())) + + index = simulator.pc.CIA.value//4 + while index < len(instructions): + ins, code = instructions[index] + + print("0x{:X}".format(ins & 0xffffffff)) + print(code) + + # ask the decoder to decode this binary data (endian'd) + yield pdecode2.dec.bigendian.eq(bigendian) # little / big? + yield instruction.eq(ins) # raw binary instr. + yield Settle() + fn_unit = yield pdecode2.e.do.fn_unit + self.assertEqual(fn_unit, Function.SHIFT_ROT.value) + yield from set_alu_inputs(alu, pdecode2, simulator) + yield + opname = code.split(' ')[0] + yield from simulator.call(opname) + index = simulator.pc.CIA.value//4 + + vld = yield alu.n.valid_o + while not vld: + yield + vld = yield alu.n.valid_o + yield + alu_out = yield alu.n.data_o.o.data + + yield from self.check_alu_outputs(alu, pdecode2, + simulator, code) + def run_all(self): m = Module() comb = m.d.comb @@ -205,67 +261,52 @@ class TestRunner(FHDLTestCase): sim = Simulator(m) sim.add_clock(1e-6) + def process(): for test in self.test_data: print(test.name) program = test.program - self.subTest(test.name) - simulator = ISA(pdecode2, test.regs, test.sprs, 0) - gen = program.generate_instructions() - instructions = list(zip(gen, program.assembly.splitlines())) - - index = simulator.pc.CIA.value//4 - while index < len(instructions): - ins, code = instructions[index] - - print("0x{:X}".format(ins & 0xffffffff)) - print(code) - - # ask the decoder to decode this binary data (endian'd) - yield pdecode2.dec.bigendian.eq(0) # little / big? - yield instruction.eq(ins) # raw binary instr. - yield Settle() - fn_unit = yield pdecode2.e.fn_unit - self.assertEqual(fn_unit, Function.SHIFT_ROT.value) - yield from set_alu_inputs(alu, pdecode2, simulator) - yield from set_extra_alu_inputs(alu, pdecode2, simulator) - yield - opname = code.split(' ')[0] - yield from simulator.call(opname) - index = simulator.pc.CIA.value//4 - - vld = yield alu.n.valid_o - while not vld: - yield - vld = yield alu.n.valid_o - yield - alu_out = yield alu.n.data_o.o - out_reg_valid = yield pdecode2.e.write_reg.ok - if out_reg_valid: - write_reg_idx = yield pdecode2.e.write_reg.data - expected = simulator.gpr(write_reg_idx).value - msg = f"expected {expected:x}, actual: {alu_out:x}" - self.assertEqual(expected, alu_out, msg) - yield from self.check_extra_alu_outputs(alu, pdecode2, - simulator) + with self.subTest(test.name): + yield from self.execute(alu, instruction, pdecode2, test) sim.add_sync_process(process) - with sim.write_vcd("simulator.vcd", "simulator.gtkw", - traces=[]): + print(dir(sim)) + if cxxsim: sim.run() + else: + with sim.write_vcd("shift_rot_simulator.vcd"): + sim.run() + + def check_alu_outputs(self, alu, dec2, sim, code): - def check_extra_alu_outputs(self, alu, dec2, sim): - rc = yield dec2.e.rc.data + rc = yield dec2.e.do.rc.data + cridx_ok = yield dec2.e.write_cr.ok + cridx = yield dec2.e.write_cr.data + + print("check extra output", repr(code), cridx_ok, cridx) if rc: - cr_expected = sim.crl[0].get_range().value - cr_actual = yield alu.n.data_o.cr0 - self.assertEqual(cr_expected, cr_actual) + self.assertEqual(cridx, 0, code) + + sim_o = {} + res = {} + + yield from ALUHelpers.get_cr_a(res, alu, dec2) + yield from ALUHelpers.get_xer_ca(res, alu, dec2) + yield from ALUHelpers.get_int_o(res, alu, dec2) + + yield from ALUHelpers.get_sim_int_o(sim_o, sim, dec2) + yield from ALUHelpers.get_wr_sim_cr_a(sim_o, sim, dec2) + yield from ALUHelpers.get_wr_sim_xer_ca(sim_o, sim, dec2) + + ALUHelpers.check_cr_a(self, res, sim_o, "CR%d %s" % (cridx, code)) + ALUHelpers.check_xer_ca(self, res, sim_o, code) + ALUHelpers.check_int_o(self, res, sim_o, code) if __name__ == "__main__": unittest.main(exit=False) suite = unittest.TestSuite() - suite.addTest(TestRunner(test_data)) + suite.addTest(TestRunner(ShiftRotTestCase().test_data)) runner = unittest.TextTestRunner() runner.run(suite)