X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fsoc%2Ffu%2Fshift_rot%2Ftest%2Ftest_pipe_caller.py;h=cfa1c67492d2f0b7b7b01a0445a3c29f05cbfb66;hb=dbc3d7a15bd8db75dc9411d698b1b5fc8fb173f5;hp=e84ebf04cdd1c766d5443d9f5e6aff8441179fba;hpb=cf16a11c352b01e05dcd698d7a6fd29b5492b7b9;p=soc.git diff --git a/src/soc/fu/shift_rot/test/test_pipe_caller.py b/src/soc/fu/shift_rot/test/test_pipe_caller.py index e84ebf04..cfa1c674 100644 --- a/src/soc/fu/shift_rot/test/test_pipe_caller.py +++ b/src/soc/fu/shift_rot/test/test_pipe_caller.py @@ -1,32 +1,23 @@ import random from soc.fu.shift_rot.pipe_data import ShiftRotPipeSpec -from soc.fu.alu.alu_input_record import CompALUOpSubset from soc.fu.shift_rot.pipeline import ShiftRotBasePipe -from soc.fu.test.common import TestAccumulatorBase, TestCase, ALUHelpers -from soc.config.endian import bigendian -from soc.decoder.isa.all import ISA -from soc.simulator.program import Program -from soc.decoder.selectable_int import SelectableInt -from soc.decoder.power_enums import (XER_bits, Function, CryIn) -from soc.decoder.power_decoder2 import (PowerDecode2) -from soc.decoder.power_decoder import (create_pdecode) -from soc.decoder.isa.caller import ISACaller, special_sprs +from openpower.test.common import TestAccumulatorBase, TestCase, ALUHelpers +from openpower.endian import bigendian +from openpower.decoder.isa.all import ISA +from openpower.simulator.program import Program +from openpower.decoder.power_enums import (XER_bits, Function, CryIn) +from openpower.decoder.power_decoder2 import (PowerDecode2) +from openpower.decoder.power_decoder import (create_pdecode) import unittest from nmigen.cli import rtlil from nmigen import Module, Signal -from nmigen.back.pysim import Delay, Settle -# NOTE: to use this (set to True), at present it is necessary to check -# out the cxxsim nmigen branch -cxxsim = False -if cxxsim: - try: - from nmigen.sim.cxxsim import Simulator - except ImportError: - print("nope, sorry, have to use nmigen cxxsim branch for now") - cxxsim = False - from nmigen.back.pysim import Simulator -else: - from nmigen.back.pysim import Simulator + +# NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell +# Also, check out the cxxsim nmigen branch, and latest yosys from git +from nmutil.sim_tmp_alternative import Simulator, Settle + +from openpower.test.shift_rot.shift_rot_cases import ShiftRotTestCase +from openpower.test.bitmanip.bitmanip_cases import BitManipTestCase def get_cu_inputs(dec2, sim): @@ -38,8 +29,9 @@ def get_cu_inputs(dec2, sim): yield from ALUHelpers.get_sim_int_rb(res, sim, dec2) # RB yield from ALUHelpers.get_sim_int_rc(res, sim, dec2) # RC yield from ALUHelpers.get_rd_sim_xer_ca(res, sim, dec2) # XER.ca + yield from ALUHelpers.get_sim_xer_so(res, sim, dec2) # XER.so - print("inputs", res) + print("alu get_cu_inputs", res) return res @@ -47,13 +39,14 @@ def get_cu_inputs(dec2, sim): def set_alu_inputs(alu, dec2, sim): # TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43 # detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok)) - # and place it into data_i.b + # and place it into i_data.b inp = yield from get_cu_inputs(dec2, sim) yield from ALUHelpers.set_int_ra(alu, dec2, inp) yield from ALUHelpers.set_int_rb(alu, dec2, inp) yield from ALUHelpers.set_int_rc(alu, dec2, inp) yield from ALUHelpers.set_xer_ca(alu, dec2, inp) + yield from ALUHelpers.set_xer_so(alu, dec2, inp) # This test bench is a bit different than is usual. Initially when I @@ -75,128 +68,17 @@ def set_alu_inputs(alu, dec2, sim): # takes around 3 seconds -class ShiftRotTestCase(TestAccumulatorBase): - - def case_0_proof_regression_rlwnm(self): - lst = ["rlwnm 3, 1, 2, 16, 20"] - initial_regs = [0] * 32 - initial_regs[1] = 0x7ffdbffb91b906b9 - initial_regs[2] = 31 - print(initial_regs[1], initial_regs[2]) - self.add_case(Program(lst, bigendian), initial_regs) - - def case_shift(self): - insns = ["slw", "sld", "srw", "srd", "sraw", "srad"] - for i in range(20): - choice = random.choice(insns) - lst = [f"{choice} 3, 1, 2"] - initial_regs = [0] * 32 - initial_regs[1] = random.randint(0, (1 << 64)-1) - initial_regs[2] = random.randint(0, 63) - print(initial_regs[1], initial_regs[2]) - self.add_case(Program(lst, bigendian), initial_regs) - - def case_shift_arith(self): - lst = ["sraw 3, 1, 2"] - initial_regs = [0] * 32 - initial_regs[1] = random.randint(0, (1 << 64)-1) - initial_regs[2] = random.randint(0, 63) - print(initial_regs[1], initial_regs[2]) - self.add_case(Program(lst, bigendian), initial_regs) - - def case_shift_once(self): - lst = ["slw 3, 1, 4", - "slw 3, 1, 2"] - initial_regs = [0] * 32 - initial_regs[1] = 0x80000000 - initial_regs[2] = 0x40 - initial_regs[4] = 0x00 - self.add_case(Program(lst, bigendian), initial_regs) - - def case_rlwinm(self): - for i in range(10): - mb = random.randint(0, 31) - me = random.randint(0, 31) - sh = random.randint(0, 31) - lst = [f"rlwinm 3, 1, {mb}, {me}, {sh}", - #f"rlwinm. 3, 1, {mb}, {me}, {sh}" - ] - initial_regs = [0] * 32 - initial_regs[1] = random.randint(0, (1 << 64)-1) - self.add_case(Program(lst, bigendian), initial_regs) - - def case_rlwimi(self): - lst = ["rlwimi 3, 1, 5, 20, 6"] - initial_regs = [0] * 32 - initial_regs[1] = 0xdeadbeef - initial_regs[3] = 0x12345678 - self.add_case(Program(lst, bigendian), initial_regs) - - def case_rlwnm(self): - lst = ["rlwnm 3, 1, 2, 20, 6"] - initial_regs = [0] * 32 - initial_regs[1] = random.randint(0, (1 << 64)-1) - initial_regs[2] = random.randint(0, 63) - self.add_case(Program(lst, bigendian), initial_regs) - - def case_rldicl(self): - lst = ["rldicl 3, 1, 5, 20"] - initial_regs = [0] * 32 - initial_regs[1] = random.randint(0, (1 << 64)-1) - self.add_case(Program(lst, bigendian), initial_regs) - - def case_rldicr(self): - lst = ["rldicr 3, 1, 5, 20"] - initial_regs = [0] * 32 - initial_regs[1] = random.randint(0, (1 << 64)-1) - self.add_case(Program(lst, bigendian), initial_regs) - - def case_regression_extswsli(self): - lst = [f"extswsli 3, 1, 34"] - initial_regs = [0] * 32 - initial_regs[1] = 0x5678 - self.add_case(Program(lst, bigendian), initial_regs) - - def case_regression_extswsli_2(self): - lst = [f"extswsli 3, 1, 7"] - initial_regs = [0] * 32 - initial_regs[1] = 0x3ffffd7377f19fdd - self.add_case(Program(lst, bigendian), initial_regs) - - def case_regression_extswsli_3(self): - lst = [f"extswsli 3, 1, 0"] - initial_regs = [0] * 32 - #initial_regs[1] = 0x80000000fb4013e2 - #initial_regs[1] = 0xffffffffffffffff - #initial_regs[1] = 0x00000000ffffffff - initial_regs[1] = 0x0000010180122900 - #initial_regs[1] = 0x3ffffd73f7f19fdd - self.add_case(Program(lst, bigendian), initial_regs) - - def case_extswsli(self): - for i in range(40): - sh = random.randint(0, 63) - lst = [f"extswsli 3, 1, {sh}"] - initial_regs = [0] * 32 - initial_regs[1] = random.randint(0, (1 << 64)-1) - self.add_case(Program(lst, bigendian), initial_regs) - - def case_rlc(self): - insns = ["rldic", "rldicl", "rldicr"] - for i in range(20): - choice = random.choice(insns) - sh = random.randint(0, 63) - m = random.randint(0, 63) - lst = [f"{choice} 3, 1, {sh}, {m}"] - initial_regs = [0] * 32 - initial_regs[1] = random.randint(0, (1 << 64)-1) - self.add_case(Program(lst, bigendian), initial_regs) +class ShiftRotIlangCase(TestAccumulatorBase): def case_ilang(self): - pspec = ShiftRotPipeSpec(id_wid=2) + class PPspec: + XLEN = 64 + pps = PPspec() + pspec = ShiftRotPipeSpec(id_wid=2, parent_pspec=pps) + pspec.draft_bitmanip = True alu = ShiftRotBasePipe(pspec) vl = rtlil.convert(alu, ports=alu.ports()) - with open("pipeline.il", "w") as f: + with open("shift_rot_pipeline.il", "w") as f: f.write(vl) @@ -229,20 +111,20 @@ class TestRunner(unittest.TestCase): yield from set_alu_inputs(alu, pdecode2, simulator) # set valid for one cycle, propagate through pipeline... - yield alu.p.valid_i.eq(1) + yield alu.p.i_valid.eq(1) yield - yield alu.p.valid_i.eq(0) + yield alu.p.i_valid.eq(0) opname = code.split(' ')[0] yield from simulator.call(opname) index = simulator.pc.CIA.value//4 - vld = yield alu.n.valid_o + vld = yield alu.n.o_valid while not vld: yield - vld = yield alu.n.valid_o + vld = yield alu.n.o_valid yield - alu_out = yield alu.n.data_o.o.data + alu_out = yield alu.n.o_data.o.data yield from self.check_alu_outputs(alu, pdecode2, simulator, code) @@ -253,15 +135,21 @@ class TestRunner(unittest.TestCase): comb = m.d.comb instruction = Signal(32) - pdecode = create_pdecode() + fn_name = "SHIFT_ROT" + opkls = ShiftRotPipeSpec.opsubsetkls - m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode) + m.submodules.pdecode2 = pdecode2 = PowerDecode2(None, opkls, fn_name) + pdecode = pdecode2.dec - pspec = ShiftRotPipeSpec(id_wid=2) + class PPspec: + XLEN = 64 + pps = PPspec() + pspec = ShiftRotPipeSpec(id_wid=2, parent_pspec=pps) + pspec.draft_bitmanip = True m.submodules.alu = alu = ShiftRotBasePipe(pspec) - comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.e) - comb += alu.n.ready_i.eq(1) + comb += alu.p.i_data.ctx.op.eq_from_execute1(pdecode2.do) + comb += alu.n.i_ready.eq(1) comb += pdecode2.dec.raw_opcode_in.eq(instruction) sim = Simulator(m) @@ -275,16 +163,12 @@ class TestRunner(unittest.TestCase): yield from self.execute(alu, instruction, pdecode2, test) sim.add_sync_process(process) - print(dir(sim)) - if cxxsim: + with sim.write_vcd("shift_rot_simulator.vcd"): sim.run() - else: - with sim.write_vcd("shift_rot_simulator.vcd"): - sim.run() def check_alu_outputs(self, alu, dec2, sim, code): - rc = yield dec2.e.do.rc.data + rc = yield dec2.e.do.rc.rc cridx_ok = yield dec2.e.write_cr.ok cridx = yield dec2.e.write_cr.data @@ -299,10 +183,14 @@ class TestRunner(unittest.TestCase): yield from ALUHelpers.get_xer_ca(res, alu, dec2) yield from ALUHelpers.get_int_o(res, alu, dec2) + print("hw outputs", res) + yield from ALUHelpers.get_sim_int_o(sim_o, sim, dec2) yield from ALUHelpers.get_wr_sim_cr_a(sim_o, sim, dec2) yield from ALUHelpers.get_wr_sim_xer_ca(sim_o, sim, dec2) + print("sim outputs", sim_o) + ALUHelpers.check_cr_a(self, res, sim_o, "CR%d %s" % (cridx, code)) ALUHelpers.check_xer_ca(self, res, sim_o, code) ALUHelpers.check_int_o(self, res, sim_o, code) @@ -312,6 +200,8 @@ if __name__ == "__main__": unittest.main(exit=False) suite = unittest.TestSuite() suite.addTest(TestRunner(ShiftRotTestCase().test_data)) + suite.addTest(TestRunner(BitManipTestCase().test_data)) + suite.addTest(TestRunner(ShiftRotIlangCase().test_data)) runner = unittest.TextTestRunner() runner.run(suite)