X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fsoc%2Ffu%2Ftest%2Fcommon.py;h=6489f5a0d6e35aa5125f288cd309368e49ecdbdd;hb=04aad087e4493a4d39cca928c8d2f3a1461b1736;hp=009797dc7e05ab050dec3533ac5eb86881a4233d;hpb=d652efe4157cfc39bc08685a4c7b968a1d9c236e;p=soc.git

diff --git a/src/soc/fu/test/common.py b/src/soc/fu/test/common.py
index 009797dc..6489f5a0 100644
--- a/src/soc/fu/test/common.py
+++ b/src/soc/fu/test/common.py
@@ -3,14 +3,119 @@ Bugreports:
 * https://bugs.libre-soc.org/show_bug.cgi?id=361
 """
 
+import inspect
+import functools
+import types
 from soc.decoder.power_enums import XER_bits, CryIn, spr_dict
-from soc.regfile.util import fast_reg_to_spr # HACK!
-from soc.regfile.regfiles import FastRegs
+from soc.regfile.util import fast_reg_to_spr, slow_reg_to_spr  # HACK!
+from soc.regfile.regfiles import XERRegs, FastRegs
+
+
+# TODO: make this a util routine (somewhere)
+def mask_extend(x, nbits, repeat):
+    res = 0
+    extended = (1<<repeat)-1
+    for i in range(nbits):
+        if x & (1<<i):
+            res |= extended << (i*repeat)
+    return res
+
+
+class SkipCase(Exception):
+    """Raise this exception to skip a test case.
+
+    Usually you'd use one of the skip_case* decorators.
+
+    For use with TestAccumulatorBase
+    """
+
+
+def _id(obj):
+    """identity function"""
+    return obj
+
+
+def skip_case(reason):
+    """
+    Unconditionally skip a test case.
+
+    Use like:
+        @skip_case("my reason for skipping")
+        def case_abc(self):
+            ...
+    or:
+        @skip_case
+        def case_def(self):
+            ...
+
+    For use with TestAccumulatorBase
+    """
+    def decorator(item):
+        assert not isinstance(item, type), \
+            "can't use skip_case to decorate types"
+
+        @functools.wraps(item)
+        def wrapper(*args, **kwargs):
+            raise SkipCase(reason)
+        return wrapper
+    if isinstance(reason, types.FunctionType):
+        item = reason
+        reason = ""
+        return decorator(item)
+    return decorator
+
+
+def skip_case_if(condition, reason):
+    """
+    Conditionally skip a test case.
+
+    Use like:
+        @skip_case_if(should_i_skip(), "my reason for skipping")
+        def case_abc(self):
+            ...
+
+    For use with TestAccumulatorBase
+    """
+    if condition:
+        return skip_case(reason)
+    return _id
+
+
+class TestAccumulatorBase:
+
+    def __init__(self):
+        self.test_data = []
+        # automatically identifies anything starting with "case_" and
+        # runs it.  very similar to unittest auto-identification except
+        # we need a different system
+        for n, v in self.__class__.__dict__.items():
+            if n.startswith("case_") and callable(v):
+                try:
+                    v(self)
+                except SkipCase as e:
+                    # TODO(programmerjake): translate to final test sending
+                    # skip signal to unittest. for now, just print the skipped
+                    # reason and ignore
+                    print(f"SKIPPED({n}):", str(e))
+
+    def add_case(self, prog, initial_regs=None, initial_sprs=None,
+                 initial_cr=0, initial_msr=0,
+                 initial_mem=None):
+
+        test_name = inspect.stack()[1][3]  # name of caller of this function
+        tc = TestCase(prog, test_name,
+                      regs=initial_regs, sprs=initial_sprs, cr=initial_cr,
+                      msr=initial_msr,
+                      mem=initial_mem)
+
+        self.test_data.append(tc)
 
 
 class TestCase:
     def __init__(self, program, name, regs=None, sprs=None, cr=0, mem=None,
-                       msr=0):
+                 msr=0,
+                 do_sim=True,
+                 extra_break_addr=None):
 
         self.program = program
         self.name = name
@@ -26,6 +131,9 @@ class TestCase:
         self.cr = cr
         self.mem = mem
         self.msr = msr
+        self.do_sim = do_sim
+        self.extra_break_addr = extra_break_addr
+
 
 class ALUHelpers:
 
@@ -48,6 +156,7 @@ class ALUHelpers:
         spr1_en = yield dec2.e.read_spr1.ok
         if spr1_en:
             spr1_sel = yield dec2.e.read_spr1.data
+            spr1_sel = slow_reg_to_spr(spr1_sel)
             spr1_data = sim.spr[spr1_sel].value
             res['spr1'] = spr1_data
 
@@ -73,6 +182,18 @@ class ALUHelpers:
             cridx = yield dec2.e.read_cr1.data
             res['cr_a'] = sim.crl[cridx].get_range().value
 
+    def get_sim_cr_b(res, sim, dec2):
+        cridx_ok = yield dec2.e.read_cr2.ok
+        if cridx_ok:
+            cridx = yield dec2.e.read_cr2.data
+            res['cr_b'] = sim.crl[cridx].get_range().value
+
+    def get_sim_cr_c(res, sim, dec2):
+        cridx_ok = yield dec2.e.read_cr3.ok
+        if cridx_ok:
+            cridx = yield dec2.e.read_cr3.data
+            res['cr_c'] = sim.crl[cridx].get_range().value
+
     def get_sim_int_ra(res, sim, dec2):
         # TODO: immediate RA zero
         reg1_ok = yield dec2.e.read_reg1.ok
@@ -95,7 +216,7 @@ class ALUHelpers:
     def get_rd_sim_xer_ca(res, sim, dec2):
         cry_in = yield dec2.e.do.input_carry
         xer_in = yield dec2.e.xer_in
-        if xer_in or cry_in == CryIn.CA.value:
+        if (xer_in & (1<<XERRegs.CA)) or cry_in == CryIn.CA.value:
             expected_carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
             expected_carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0
             res['xer_ca'] = expected_carry | (expected_carry32 << 1)
@@ -111,10 +232,12 @@ class ALUHelpers:
         yield alu.p.data_i.rb.eq(0)
         if 'rb' in inp:
             yield alu.p.data_i.rb.eq(inp['rb'])
+        if not hasattr(dec2.e.do, "imm_data"):
+            return
         # If there's an immediate, set the B operand to that
-        imm_ok = yield dec2.e.do.imm_data.imm_ok
+        imm_ok = yield dec2.e.do.imm_data.ok
         if imm_ok:
-            data2 = yield dec2.e.do.imm_data.imm
+            data2 = yield dec2.e.do.imm_data.data
             yield alu.p.data_i.rb.eq(data2)
 
     def set_int_rc(alu, dec2, inp):
@@ -126,24 +249,26 @@ class ALUHelpers:
     def set_xer_ca(alu, dec2, inp):
         if 'xer_ca' in inp:
             yield alu.p.data_i.xer_ca.eq(inp['xer_ca'])
-            print ("extra inputs: CA/32", bin(inp['xer_ca']))
+            print("extra inputs: CA/32", bin(inp['xer_ca']))
 
     def set_xer_ov(alu, dec2, inp):
         if 'xer_ov' in inp:
             yield alu.p.data_i.xer_ov.eq(inp['xer_ov'])
-            print ("extra inputs: OV/32", bin(inp['xer_ov']))
+            print("extra inputs: OV/32", bin(inp['xer_ov']))
 
     def set_xer_so(alu, dec2, inp):
         if 'xer_so' in inp:
             so = inp['xer_so']
-            print ("extra inputs: so", so)
+            print("extra inputs: so", so)
             yield alu.p.data_i.xer_so.eq(so)
 
     def set_msr(alu, dec2, inp):
+        print("TODO: deprecate set_msr")
         if 'msr' in inp:
             yield alu.p.data_i.msr.eq(inp['msr'])
 
     def set_cia(alu, dec2, inp):
+        print("TODO: deprecate set_cia")
         if 'cia' in inp:
             yield alu.p.data_i.cia.eq(inp['cia'])
 
@@ -177,7 +302,10 @@ class ALUHelpers:
 
     def set_full_cr(alu, dec2, inp):
         if 'full_cr' in inp:
-            yield alu.p.data_i.full_cr.eq(inp['full_cr'])
+            full_reg = yield dec2.dec_cr_in.whole_reg.data
+            full_reg_ok = yield dec2.dec_cr_in.whole_reg.ok
+            full_cr_mask = mask_extend(full_reg, 8, 4)
+            yield alu.p.data_i.full_cr.eq(inp['full_cr'] & full_cr_mask)
         else:
             yield alu.p.data_i.full_cr.eq(0)
 
@@ -233,6 +361,8 @@ class ALUHelpers:
         oe = yield dec2.e.do.oe.oe
         oe_ok = yield dec2.e.do.oe.ok
         xer_out = yield dec2.e.xer_out
+        if not (yield alu.n.data_o.xer_so.ok):
+            return
         if xer_out or (oe and oe_ok):
             res['xer_so'] = yield alu.n.data_o.xer_so.data[0]
 
@@ -240,12 +370,16 @@ class ALUHelpers:
         oe = yield dec2.e.do.oe.oe
         oe_ok = yield dec2.e.do.oe.ok
         xer_out = yield dec2.e.xer_out
+        if not (yield alu.n.data_o.xer_ov.ok):
+            return
         if xer_out or (oe and oe_ok):
             res['xer_ov'] = yield alu.n.data_o.xer_ov.data
 
     def get_xer_ca(res, alu, dec2):
         cry_out = yield dec2.e.do.output_carry
         xer_out = yield dec2.e.xer_out
+        if not (yield alu.n.data_o.xer_ca.ok):
+            return
         if xer_out or (cry_out):
             res['xer_ca'] = yield alu.n.data_o.xer_ca.data
 
@@ -287,31 +421,59 @@ class ALUHelpers:
         ok = yield dec2.e.write_spr.ok
         if ok:
             spr_num = yield dec2.e.write_spr.data
+            spr_num = slow_reg_to_spr(spr_num)
             spr_name = spr_dict[spr_num].SPR
             res['spr1'] = sim.spr[spr_name].value
 
     def get_wr_sim_xer_ca(res, sim, dec2):
+        # if not (yield alu.n.data_o.xer_ca.ok):
+        #    return
         cry_out = yield dec2.e.do.output_carry
-        if cry_out:
+        xer_out = yield dec2.e.xer_out
+        if cry_out or xer_out:
             expected_carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
             expected_carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0
             res['xer_ca'] = expected_carry | (expected_carry32 << 1)
 
+    def get_wr_sim_xer_ov(res, sim, alu, dec2):
+        oe = yield dec2.e.do.oe.oe
+        oe_ok = yield dec2.e.do.oe.ok
+        xer_out = yield dec2.e.xer_out
+        print("get_wr_sim_xer_ov", xer_out)
+        if not (yield alu.n.data_o.xer_ov.ok):
+            return
+        if xer_out or (oe and oe_ok):
+            expected_ov = 1 if sim.spr['XER'][XER_bits['OV']] else 0
+            expected_ov32 = 1 if sim.spr['XER'][XER_bits['OV32']] else 0
+            res['xer_ov'] = expected_ov | (expected_ov32 << 1)
+
+    def get_wr_sim_xer_so(res, sim, alu, dec2):
+        oe = yield dec2.e.do.oe.oe
+        oe_ok = yield dec2.e.do.oe.ok
+        xer_out = yield dec2.e.xer_out
+        if not (yield alu.n.data_o.xer_so.ok):
+            return
+        if xer_out or (oe and oe_ok):
+            res['xer_so'] = 1 if sim.spr['XER'][XER_bits['SO']] else 0
+
     def get_sim_xer_ov(res, sim, dec2):
         oe = yield dec2.e.do.oe.oe
         oe_ok = yield dec2.e.do.oe.ok
         xer_in = yield dec2.e.xer_in
-        print ("get_sim_xer_ov", xer_in)
-        if xer_in or (oe and oe_ok):
+        print("get_sim_xer_ov", xer_in)
+        if (xer_in & (1<<XERRegs.OV)) or (oe and oe_ok):
             expected_ov = 1 if sim.spr['XER'][XER_bits['OV']] else 0
             expected_ov32 = 1 if sim.spr['XER'][XER_bits['OV32']] else 0
             res['xer_ov'] = expected_ov | (expected_ov32 << 1)
 
     def get_sim_xer_so(res, sim, dec2):
+        print ("XER", sim.spr.__class__, sim.spr, sim.spr['XER'])
         oe = yield dec2.e.do.oe.oe
         oe_ok = yield dec2.e.do.oe.ok
         xer_in = yield dec2.e.xer_in
-        if xer_in or (oe and oe_ok):
+        rc = yield dec2.e.do.rc.rc
+        rc_ok = yield dec2.e.do.rc.ok
+        if (xer_in & (1<<XERRegs.SO)) or (oe and oe_ok) or (rc and rc_ok):
             res['xer_so'] = 1 if sim.spr['XER'][XER_bits['SO']] else 0
 
     def check_slow_spr1(dut, res, sim_o, msg):
@@ -346,6 +508,13 @@ class ALUHelpers:
         if 'o' in res:
             expected = sim_o['o']
             alu_out = res['o']
+            print(f"expected int sim {expected:x}, actual: {alu_out:x}")
+            dut.assertEqual(expected, alu_out, msg)
+
+    def check_msr(dut, res, sim_o, msg):
+        if 'msr' in res:
+            expected = sim_o['msr']
+            alu_out = res['msr']
             print(f"expected {expected:x}, actual: {alu_out:x}")
             dut.assertEqual(expected, alu_out, msg)
 
@@ -360,27 +529,26 @@ class ALUHelpers:
         if 'cr_a' in res:
             cr_expected = sim_o['cr_a']
             cr_actual = res['cr_a']
-            print ("CR", cr_expected, cr_actual)
+            print("CR", cr_expected, cr_actual)
             dut.assertEqual(cr_expected, cr_actual, msg)
 
     def check_xer_ca(dut, res, sim_o, msg):
         if 'xer_ca' in res:
             ca_expected = sim_o['xer_ca']
             ca_actual = res['xer_ca']
-            print ("CA", ca_expected, ca_actual)
+            print("CA", ca_expected, ca_actual)
             dut.assertEqual(ca_expected, ca_actual, msg)
 
     def check_xer_ov(dut, res, sim_o, msg):
         if 'xer_ov' in res:
             ov_expected = sim_o['xer_ov']
             ov_actual = res['xer_ov']
-            print ("OV", ov_expected, ov_actual)
+            print("OV", ov_expected, ov_actual)
             dut.assertEqual(ov_expected, ov_actual, msg)
 
     def check_xer_so(dut, res, sim_o, msg):
         if 'xer_so' in res:
             so_expected = sim_o['xer_so']
             so_actual = res['xer_so']
-            print ("SO", so_expected, so_actual)
+            print("SO", so_expected, so_actual)
             dut.assertEqual(so_expected, so_actual, msg)
-