X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fsoc%2Ffu%2Ftrap%2Fmain_stage.py;h=3b9c7bed1a40da8d081a1bd0a87323f897462fce;hb=10f4200e58562d6070203afdddea1dc0c0eb5f88;hp=d838b150fd995108cca59824901ccd1df1c9eecd;hpb=8c9393e916da373a4e2c23afdf6c17557462d97f;p=soc.git diff --git a/src/soc/fu/trap/main_stage.py b/src/soc/fu/trap/main_stage.py index d838b150..3b9c7bed 100644 --- a/src/soc/fu/trap/main_stage.py +++ b/src/soc/fu/trap/main_stage.py @@ -1,5 +1,9 @@ """Trap Pipeline +Deals with td/tw/tdi/twi as well as mfmsr/mtmsr, sc and rfid. addpcis TODO. +Also used generally for interrupts (as a micro-coding mechanism) by +actually modifying the decoded instruction in PowerDecode2. + * https://bugs.libre-soc.org/show_bug.cgi?id=325 * https://bugs.libre-soc.org/show_bug.cgi?id=344 * https://libre-soc.org/openpower/isa/fixedtrap/ @@ -9,35 +13,125 @@ from nmigen import (Module, Signal, Cat, Mux, Const, signed) from nmutil.pipemodbase import PipeModBase from nmutil.extend import exts from soc.fu.trap.pipe_data import TrapInputData, TrapOutputData -from soc.decoder.power_enums import InternalOp +from soc.fu.branch.main_stage import br_ext +from openpower.decoder.power_enums import MicrOp +from soc.experiment.mem_types import LDSTException -from soc.decoder.power_fields import DecodeFields -from soc.decoder.power_fieldsn import SignalBitRange +from openpower.decoder.power_fields import DecodeFields +from openpower.decoder.power_fieldsn import SignalBitRange + +from openpower.consts import MSR, PI, TT, field, field_slice + + +def msr_copy(msr_o, msr_i, zero_me=True): + """msr_copy (also used to copy relevant bits into SRR1) + + ISA says this: + Defined MSR bits are classified as either full func tion or partial + function. Full function MSR bits are saved in SRR1 or HSRR1 when + an interrupt other than a System Call Vectored interrupt occurs and + restored by rfscv, rfid, or hrfid, while partial function MSR bits + are not saved or restored. Full function MSR bits lie in the range + 0:32, 37:41, and 48:63, and partial function MSR bits lie in the + range 33:36 and 42:47. (Note this is IBM bit numbering). + """ + l = [] + if zero_me: + l.append(msr_o.eq(0)) + for stt, end in [(0,16), (22, 27), (31, 64)]: + l.append(msr_o[stt:end].eq(msr_i[stt:end])) + return l + + +def msr_check_pr(m, d_in, msr): + """msr_check_pr: checks "problem state" + """ + comb = m.d.comb + with m.If(d_in[MSR.PR]): + comb += msr[MSR.EE].eq(1) # set external interrupt bit + comb += msr[MSR.IR].eq(1) # set instruction relocation bit + comb += msr[MSR.DR].eq(1) # set data relocation bit -# TODO at some point move these to their own module (for use elsewhere) -# TODO: turn these into python constants (just "MSR_SF = 63-0 # comment" etc.) -""" - Listed in V3.0B Book III Chap 4.2.1 - -- MSR bit numbers - constant MSR_SF : integer := (63 - 0); -- Sixty-Four bit mode - constant MSR_HV : integer := (63 - 3); -- Hypervisor state - constant MSR_S : integer := (63 - 41); -- Secure state - constant MSR_EE : integer := (63 - 48); -- External interrupt Enable - constant MSR_PR : integer := (63 - 49); -- PRoblem state - constant MSR_FP : integer := (63 - 50); -- FP available - constant MSR_ME : integer := (63 - 51); -- Machine Check int enable - constant MSR_IR : integer := (63 - 58); -- Instruction Relocation - constant MSR_DR : integer := (63 - 59); -- Data Relocation - constant MSR_PMM : integer := (63 - 60); -- Performance Monitor Mark - constant MSR_RI : integer := (63 - 62); -- Recoverable Interrupt - constant MSR_LE : integer := (63 - 63); -- Little Endian -""" class TrapMainStage(PipeModBase): def __init__(self, pspec): super().__init__(pspec, "main") self.fields = DecodeFields(SignalBitRange, [self.i.ctx.op.insn]) self.fields.create_specs() + self.kaivb = Signal(64) # KAIVB SPR + + def trap(self, m, trap_addr, return_addr): + """trap. sets new PC, stores MSR and old PC in SRR1 and SRR0 + """ + comb = m.d.comb + op = self.i.ctx.op + msr_i = op.msr + svstate_i = op.svstate + + exc = LDSTException("trapexc") + comb += exc.eq(op.ldst_exc) + srr1_i = exc.srr1 # new SRR1 bits come from exception + nia_o = self.o.nia + svsrr0_o, srr0_o, srr1_o = self.o.svsrr0, self.o.srr0, self.o.srr1 + + # trap address, including KAIVB override + comb += nia_o.data.eq(trap_addr) + comb += nia_o.data[13:].eq(self.kaivb[13:]) + comb += nia_o.ok.eq(1) + + # addr to begin from on return + comb += srr0_o.data.eq(return_addr) + comb += srr0_o.ok.eq(1) + + # take a copy of the current MSR into SRR1, but first copy old SRR1 + # this preserves the bits of SRR1 that are not supposed to change: + # MSR.IR,DR,PMM,RI,LE (0-5) and MR,FP,ME,FE0 (11-14) + # i would suggest reading v3.0C p1063 Book III section 7.2.1 for + # advice but it's so obscure and indirect, that it's just easier + # to copy microwatt behaviour. see writeback.vhdl + # IMPORTANT: PowerDecoder2 needed to actually read SRR1 for + # it to have the contents *of* SRR1 to copy over! + comb += msr_copy(srr1_o.data, msr_i, False) # old MSR + comb += srr1_o.data[16:22].eq(srr1_i[0:6]) # IR,DR,PMM,RI,LE + comb += srr1_o.data[27:31].eq(srr1_i[11:15]) # MR,FP,ME,FE0 + comb += srr1_o.ok.eq(1) + + # take a copy of the current SVSTATE into SVSRR0 + comb += svsrr0_o.data.eq(svstate_i) # old SVSTATE + comb += svsrr0_o.ok.eq(1) + + def msr_exception(self, m, trap_addr, msr_hv=None): + """msr_exception - sets bits in MSR specific to an exception. + the full list of what needs to be done is given in V3.0B + Book III Section 6.5 p1063 however it turns out that for the + majority of cases (microwatt showing the way, here), all these + bits are all set by all (implemented) interrupt types. this + may change in the future, hence the (unused) trap_addr argument + """ + comb = m.d.comb + op = self.i.ctx.op + msr_i, msr_o = op.msr, self.o.msr + comb += msr_o.data.eq(msr_i) # copy msr, first, then modify + comb += msr_o.data[MSR.SF].eq(1) + comb += msr_o.data[MSR.EE].eq(0) + comb += msr_o.data[MSR.PR].eq(0) + comb += msr_o.data[MSR.IR].eq(0) + comb += msr_o.data[MSR.DR].eq(0) + comb += msr_o.data[MSR.RI].eq(0) + comb += msr_o.data[MSR.LE].eq(1) + comb += msr_o.data[MSR.FE0].eq(0) + comb += msr_o.data[MSR.FE1].eq(0) + comb += msr_o.data[MSR.VSX].eq(0) + comb += msr_o.data[MSR.TM].eq(0) + comb += msr_o.data[MSR.VEC].eq(0) + comb += msr_o.data[MSR.FP].eq(0) + comb += msr_o.data[MSR.PMM].eq(0) + comb += msr_o.data[MSR.TEs].eq(0) # this is only 2 bits + comb += msr_o.data[MSR.TEe].eq(0) # so just zero them both + comb += msr_o.data[MSR.UND].eq(0) + if msr_hv is not None: + comb += msr_o.data[MSR.HV].eq(msr_hv) + comb += msr_o.ok.eq(1) def ispec(self): return TrapInputData(self.pspec) @@ -47,11 +141,17 @@ class TrapMainStage(PipeModBase): def elaborate(self, platform): m = Module() - comb = m.d.comb + comb, sync = m.d.comb, m.d.sync op = self.i.ctx.op - a_i, b_i, cia_i, msr_i = self.i.a, self.i.b, self.i.cia, self.i.msr - o, msr_o, nia_o = self.o.o, self.o.msr, self.o.nia - srr0_o, srr1_o = self.o.srr0, self.o.srr1 + + # convenience variables + a_i, b_i = self.i.a, self.i.b + cia_i, msr_i, svstate_i = op.cia, op.msr, op.svstate + srr0_i, srr1_i, svsrr0_i = self.i.srr0, self.i.srr1, self.i.svsrr0 + o = self.o.o + msr_o, nia_o, svstate_o = self.o.msr, self.o.nia, self.o.svstate + srr0_o, srr1_o, svsrr0_o = self.o.srr0, self.o.srr1, self.o.svsrr0 + traptype, trapaddr = op.traptype, op.trapaddr # take copy of D-Form TO field i_fields = self.fields.FormD @@ -92,122 +192,186 @@ class TrapMainStage(PipeModBase): # They're in reverse bit order because POWER. # Check V3.0B Book 1, Appendix C.6 for chart - trap_bits = Signal(5) + trap_bits = Signal(5, reset_less=True) comb += trap_bits.eq(Cat(gt_u, lt_u, equal, gt_s, lt_s)) # establish if the trap should go ahead (any tests requested in TO) - should_trap = Signal() - comb += should_trap.eq((trap_bits & to).any()) + # or if traptype is set already + should_trap = Signal(reset_less=True) + comb += should_trap.eq((trap_bits & to).any() | traptype.any()) # TODO: some #defines for the bits n stuff. - with m.Switch(op): - #### trap #### - with m.Case(InternalOp.OP_TRAP): - """ - -- trap instructions (tw, twi, td, tdi) - if or (trapval and insn_to(e_in.insn)) = '1' then - -- generate trap-type program interrupt - exception := '1'; - ctrl_tmp.irq_nia <= std_logic_vector(to_unsigned(16#700#, 64)); - ctrl_tmp.srr1 <= msr_copy(ctrl.msr); - -- set bit 46 to say trap occurred - ctrl_tmp.srr1(63 - 46) <= '1'; - """ + with m.Switch(op.insn_type): + + ############## + # KAIVB https://bugs.libre-soc.org/show_bug.cgi?id=859 + + with m.Case(MicrOp.OP_MTSPR): + sync += self.kaivb.eq(a_i) + + with m.Case(MicrOp.OP_MFSPR): + comb += o.data.eq(self.kaivb) + comb += o.ok.eq(1) + + ############### + # TDI/TWI/TD/TW. v3.0B p90-91 + + with m.Case(MicrOp.OP_TRAP): + # trap instructions (tw, twi, td, tdi) with m.If(should_trap): - comb += self.o.nia.data.eq(0x700) # trap address - comb += self.o.nia.ok.eq(1) - comb += self.o.srr1.data.eq(self.i.msr) # old MSR - comb += self.o.srr1.data[63-46].eq(1) # XXX which bit? - comb += self.o.srr1.ok.eq(1) - comb += self.o.srr0.data.eq(self.i.cia) # old PC - comb += self.o.srr0.ok.eq(1) - - # move to SPR - with m.Case(InternalOp.OP_MTMSR): - # TODO: some of the bits need zeroing? - """ - if e_in.insn(16) = '1' then <-- this is X-form field "L". - -- just update EE and RI - ctrl_tmp.msr(MSR_EE) <= c_in(MSR_EE); - ctrl_tmp.msr(MSR_RI) <= c_in(MSR_RI); - else - -- Architecture says to leave out bits 3 (HV), 51 (ME) - -- and 63 (LE) (IBM bit numbering) - ctrl_tmp.msr(63 downto 61) <= c_in(63 downto 61); - ctrl_tmp.msr(59 downto 13) <= c_in(59 downto 13); - ctrl_tmp.msr(11 downto 1) <= c_in(11 downto 1); - if c_in(MSR_PR) = '1' then - ctrl_tmp.msr(MSR_EE) <= '1'; - ctrl_tmp.msr(MSR_IR) <= '1'; - ctrl_tmp.msr(MSR_DR) <= '1'; - """ - # TODO translate this: - # L = self.fields.FormX[0:-1] - # if e_in.insn(16) = '1' then <-- this is X-form field "L". - # -- just update EE and RI - # ctrl_tmp.msr(MSR_EE) <= c_in(MSR_EE); - # ctrl_tmp.msr(MSR_RI) <= c_in(MSR_RI); + # generate trap-type program interrupt + self.trap(m, trapaddr<<4, cia_i) + with m.If(traptype == 0): + # say trap occurred (see 3.0B Book III 6.5.9 p1074-6) + comb += srr1_o.data[PI.TRAP].eq(1) + with m.If(traptype & TT.PRIV): + comb += srr1_o.data[PI.PRIV].eq(1) + with m.If(traptype & TT.FP): + comb += srr1_o.data[PI.FP].eq(1) + with m.If(traptype & TT.ADDR): + comb += srr1_o.data[PI.ADR].eq(1) + with m.If((traptype & TT.MEMEXC).bool() & + (trapaddr == 0x400)): + # Instruction Storage Interrupt (ISI - 0x400) + # v3.0C Book III Chap 7.5.5 p1085 + # decode exception bits, store in SRR1 + exc = LDSTException("trapexc") + comb += exc.eq(op.ldst_exc) + comb += srr1_o.data[PI.INVALID].eq(exc.invalid) + comb += srr1_o.data[PI.PERMERR].eq(exc.perm_error) + comb += srr1_o.data[PI.ILLEG].eq(exc.badtree) + comb += srr1_o.data[PI.PRIV].eq(exc.rc_error) + with m.If(traptype & TT.EINT): + # do nothing unusual? see 3.0B Book III 6.5.7 p1073 + pass + with m.If(traptype & TT.DEC): + # do nothing unusual? + pass + with m.If(traptype & TT.ILLEG): + comb += srr1_o.data[PI.ILLEG].eq(1) + comb += srr1_o.ok.eq(1) + + # when SRR1 is written to, update MSR bits + self.msr_exception(m, trapaddr) + + # and store SVSTATE in SVSRR0 + comb += svsrr0_o.data.eq(svstate_i) + comb += svsrr0_o.ok.eq(1) + + ################### + # MTMSR/D. v3.0B p TODO - move to MSR + + with m.Case(MicrOp.OP_MTMSRD, MicrOp.OP_MTMSR): + # L => bit 16 in LSB0, bit 15 in MSB0 order + L = self.fields.FormX.L1[0:1] # X-Form field L1 + # start with copy of msr + comb += msr_o.eq(msr_i) + with m.If(L): + # just update RI..EE + comb += msr_o.data[MSR.RI].eq(a_i[MSR.RI]) + comb += msr_o.data[MSR.EE].eq(a_i[MSR.EE]) with m.Else(): - for stt, end in [(1,12), (13, 60), (61, 64)]: - comb += self.o.msr.data[stt:end].eq(a[stt:end]) - with m.If(a[MSR_PR]): - self.o.msr[MSR_EE].eq(1) - self.o.msr[MSR_IR].eq(1) - self.o.msr[MSR_DR].eq(1) - comb += self.o.msr.ok.eq(1) - - # move from SPR - with m.Case(InternalOp.OP_MFMSR): - # TODO: some of the bits need zeroing? apparently not - """ - when OP_MFMSR => - result := ctrl.msr; - result_en := '1'; - """ - comb += self.o.o.data.eq(self.i.msr) - comb += self.o.o.ok.eq(1) - - with m.Case(InternalOp.OP_RFID): - """ - # XXX f_out.virt_mode <= b_in(MSR_IR) or b_in(MSR_PR); - # XXX f_out.priv_mode <= not b_in(MSR_PR); - f_out.redirect_nia <= a_in(63 downto 2) & "00"; -- srr0 - -- Can't use msr_copy here because the partial function MSR - -- bits should be left unchanged, not zeroed. - ctrl_tmp.msr(63 downto 31) <= b_in(63 downto 31); - ctrl_tmp.msr(26 downto 22) <= b_in(26 downto 22); - ctrl_tmp.msr(15 downto 0) <= b_in(15 downto 0); - if b_in(MSR_PR) = '1' then - ctrl_tmp.msr(MSR_EE) <= '1'; - ctrl_tmp.msr(MSR_IR) <= '1'; - ctrl_tmp.msr(MSR_DR) <= '1'; - end if; - """ - # TODO translate this, import and use br_ext from branch stage - # f_out.redirect_nia <= a_in(63 downto 2) & "00"; -- srr0 - for stt, end in [(0,16), (22, 27), (31, 64)]: - comb += self.o.msr.data[stt:end].eq(a[stt:end]) - with m.If(a[MSR_PR]): - self.o.msr[MSR_EE].eq(1) - self.o.msr[MSR_IR].eq(1) - self.o.msr[MSR_DR].eq(1) - comb += self.o.msr.ok.eq(1) - - # TODO - with m.Case(InternalOp.OP_SC): - """ - # TODO: scv must generate illegal instruction. this is - # the decoder's job, not ours, here. - ctrl_tmp.irq_nia <= std_logic_vector(to_unsigned(16#C00#, 64)); - ctrl_tmp.srr1 <= msr_copy(ctrl.msr); - """ - comb += self.o.nia.eq(0xC00) # trap address - comb += self.o.nia.ok.eq(1) - # TODO translate this line: ctrl_tmp.srr1 <= msr_copy(ctrl.msr); - comb += self.o.srr1.ok.eq(1) + # Architecture says to leave out bits 3 (HV), 51 (ME) + # and 63 (LE) (IBM bit numbering) + with m.If(op.insn_type == MicrOp.OP_MTMSRD): + # not MSB0 notation here! + for stt, end in [(1,12), (13, 60), (61, 64)]: + comb += msr_o.data[stt:end].eq(a_i[stt:end]) + # put *back* bits 29-31 (MSB0 notation) + bits = field_slice(29, 31) + with m.If((msr_i[bits] == Const(0b010, 3)) & + (a_i[bits] == Const(0b000, 3))): + comb += msr_o.data[bits].eq(msr_i[bits]) + + with m.Else(): + # mtmsr - 32-bit, only room for bottom 32 LSB flags + for stt, end in [(1,12), (13, 32)]: + comb += msr_o.data[stt:end].eq(a_i[stt:end]) + # check problem state: if set, not permitted to set EE,IR,DR + msr_check_pr(m, a_i, msr_o.data) + + # Per https://bugs.libre-soc.org/show_bug.cgi?id=325#c123, + # this actually *is* in the microwatt code now. + # + # hypervisor stuff. here: bits 3 (HV) and 51 (ME) were + # copied over by msr_copy but if HV was not set we need + # the *original* (msr_i) bits + # XXX taking this out to see what happens when running + # linux-5.7 microwatt buildroot. microwatt does not + # implement HV, so this is unlikely to work. 0x900 + # linux kernel exception handling tends to support this + # with m.If(~msr_i[MSR.HV]): + # comb += msr_o.data[MSR.HV].eq(msr_i[MSR.HV]) + # comb += msr_o.data[MSR.ME].eq(msr_i[MSR.ME]) + + comb += msr_o.ok.eq(1) + + ################### + # MFMSR. v3.0B p TODO - move from MSR + + with m.Case(MicrOp.OP_MFMSR): + # some of the bits need zeroing? apparently not + comb += o.data.eq(msr_i) + comb += o.ok.eq(1) + + ################### + # RFID. v3.0B p955 + + with m.Case(MicrOp.OP_RFID): + + # return addr was in srr0 + comb += nia_o.data.eq(br_ext(srr0_i[2:])) + comb += nia_o.ok.eq(1) + + # svstate was in svsrr0 + comb += svstate_o.data.eq(svstate_i) + comb += svstate_o.ok.eq(1) + + # MSR was in srr1: copy it over, however *caveats below* + comb += msr_copy(msr_o.data, srr1_i, zero_me=False) # don't zero + + if False: # XXX no - not doing hypervisor yet + with m.If(~self.i.ctx.op.insn[9]): # XXX BAD HACK! (hrfid) + with m.If(field(msr_i, 3)): # HV + comb += field(msr_o, 51).eq(field(srr1_i, 51)) # ME + with m.Else(): + comb += field(msr_o, 51).eq(field(msr_i, 51)) # ME + else: + # same as microwatt: treat MSR.ME rfid same as hrfid + comb += field(msr_o, 51).eq(field(srr1_i, 51)) # ME + + # check problem state: if set, not permitted to set EE,IR,DR + msr_check_pr(m, srr1_i, msr_o.data) + + # don't understand but it's in the spec. again: bits 32-34 + # are copied from srr1_i and need *restoring* to msr_i + + bits = field_slice(29, 31) # bits 29, 30, 31 (Power notation) + with m.If((msr_i[bits] == Const(0b010, 3)) & + (srr1_i[bits] == Const(0b000, 3))): + comb += msr_o.data[bits].eq(msr_i[bits]) + + comb += msr_o.ok.eq(1) + + ################# + # SC. v3.0B p952 + + with m.Case(MicrOp.OP_SC): + # scv is not covered here. currently an illegal instruction. + # raising "illegal" is the decoder's job, not ours, here. + + # According to V3.0B, Book II, section 3.3.1, the System Call + # instruction allows you to trap directly into the hypervisor + # if the opcode's LEV sub-field is equal to 1. + # however we are following *microwatt* - which has + # not implemented hypervisor. + + # jump to the trap address, return at cia+4 + self.trap(m, 0xc00, cia_i+4) + self.msr_exception(m, 0xc00) # TODO (later) - #with m.Case(InternalOp.OP_ADDPCIS): + #with m.Case(MicrOp.OP_ADDPCIS): # pass comb += self.o.ctx.eq(self.i.ctx)