X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fsoc%2Ffu%2Ftrap%2Fmain_stage.py;h=ee09d9ec070f53169f9874988365b62a961ec2d2;hb=f5234aa51aed718d045e9a1c61247eb4480a6f52;hp=d838b150fd995108cca59824901ccd1df1c9eecd;hpb=8c9393e916da373a4e2c23afdf6c17557462d97f;p=soc.git diff --git a/src/soc/fu/trap/main_stage.py b/src/soc/fu/trap/main_stage.py index d838b150..ee09d9ec 100644 --- a/src/soc/fu/trap/main_stage.py +++ b/src/soc/fu/trap/main_stage.py @@ -1,5 +1,9 @@ """Trap Pipeline +Deals with td/tw/tdi/twi as well as mfmsr/mtmsr, sc and rfid. addpcis TODO. +Also used generally for interrupts (as a micro-coding mechanism) by +actually modifying the decoded instruction in PowerDecode2. + * https://bugs.libre-soc.org/show_bug.cgi?id=325 * https://bugs.libre-soc.org/show_bug.cgi?id=344 * https://libre-soc.org/openpower/isa/fixedtrap/ @@ -9,29 +13,45 @@ from nmigen import (Module, Signal, Cat, Mux, Const, signed) from nmutil.pipemodbase import PipeModBase from nmutil.extend import exts from soc.fu.trap.pipe_data import TrapInputData, TrapOutputData +from soc.fu.branch.main_stage import br_ext from soc.decoder.power_enums import InternalOp from soc.decoder.power_fields import DecodeFields from soc.decoder.power_fieldsn import SignalBitRange -# TODO at some point move these to their own module (for use elsewhere) -# TODO: turn these into python constants (just "MSR_SF = 63-0 # comment" etc.) -""" - Listed in V3.0B Book III Chap 4.2.1 - -- MSR bit numbers - constant MSR_SF : integer := (63 - 0); -- Sixty-Four bit mode - constant MSR_HV : integer := (63 - 3); -- Hypervisor state - constant MSR_S : integer := (63 - 41); -- Secure state - constant MSR_EE : integer := (63 - 48); -- External interrupt Enable - constant MSR_PR : integer := (63 - 49); -- PRoblem state - constant MSR_FP : integer := (63 - 50); -- FP available - constant MSR_ME : integer := (63 - 51); -- Machine Check int enable - constant MSR_IR : integer := (63 - 58); -- Instruction Relocation - constant MSR_DR : integer := (63 - 59); -- Data Relocation - constant MSR_PMM : integer := (63 - 60); -- Performance Monitor Mark - constant MSR_RI : integer := (63 - 62); -- Recoverable Interrupt - constant MSR_LE : integer := (63 - 63); -- Little Endian -""" +from soc.decoder.power_decoder2 import (TT_FP, TT_PRIV, TT_TRAP, TT_ADDR, + TT_ILLEG) +from soc.consts import MSR, PI + + +def msr_copy(msr_o, msr_i, zero_me=True): + """msr_copy + ISA says this: + Defined MSR bits are classified as either full func tion or partial + function. Full function MSR bits are saved in SRR1 or HSRR1 when + an interrupt other than a System Call Vectored interrupt occurs and + restored by rfscv, rfid, or hrfid, while partial function MSR bits + are not saved or restored. Full function MSR bits lie in the range + 0:32, 37:41, and 48:63, and partial function MSR bits lie in the + range 33:36 and 42:47. (Note this is IBM bit numbering). + """ + l = [] + if zero_me: + l.append(msr_o.eq(0)) + for stt, end in [(0,16), (22, 27), (31, 64)]: + l.append(msr_o[stt:end].eq(msr_i[stt:end])) + return l + + +def msr_check_pr(m, msr): + """msr_check_pr: checks "problem state" + """ + comb = m.d.comb + with m.If(msr[MSR.PR]): + comb += msr[MSR.EE].eq(1) # set external interrupt bit + comb += msr[MSR.IR].eq(1) # set instruction relocation bit + comb += msr[MSR.DR].eq(1) # set data relocation bit + class TrapMainStage(PipeModBase): def __init__(self, pspec): @@ -39,6 +59,25 @@ class TrapMainStage(PipeModBase): self.fields = DecodeFields(SignalBitRange, [self.i.ctx.op.insn]) self.fields.create_specs() + def trap(self, m, trap_addr, return_addr): + """trap. sets new PC, stores MSR and old PC in SRR1 and SRR0 + """ + comb = m.d.comb + msr_i = self.i.msr + nia_o, srr0_o, srr1_o = self.o.nia, self.o.srr0, self.o.srr1 + + # trap address + comb += nia_o.data.eq(trap_addr) + comb += nia_o.ok.eq(1) + + # addr to begin from on return + comb += srr0_o.data.eq(return_addr) + comb += srr0_o.ok.eq(1) + + # take a copy of the current MSR in SRR1 + comb += msr_copy(srr1_o.data, msr_i) # old MSR + comb += srr1_o.ok.eq(1) + def ispec(self): return TrapInputData(self.pspec) @@ -49,9 +88,13 @@ class TrapMainStage(PipeModBase): m = Module() comb = m.d.comb op = self.i.ctx.op + + # convenience variables a_i, b_i, cia_i, msr_i = self.i.a, self.i.b, self.i.cia, self.i.msr + srr0_i, srr1_i = self.i.srr0, self.i.srr1 o, msr_o, nia_o = self.o.o, self.o.msr, self.o.nia srr0_o, srr1_o = self.o.srr0, self.o.srr1 + traptype, trapaddr = op.traptype, op.trapaddr # take copy of D-Form TO field i_fields = self.fields.FormD @@ -92,119 +135,85 @@ class TrapMainStage(PipeModBase): # They're in reverse bit order because POWER. # Check V3.0B Book 1, Appendix C.6 for chart - trap_bits = Signal(5) + trap_bits = Signal(5, reset_less=True) comb += trap_bits.eq(Cat(gt_u, lt_u, equal, gt_s, lt_s)) # establish if the trap should go ahead (any tests requested in TO) - should_trap = Signal() - comb += should_trap.eq((trap_bits & to).any()) + # or if traptype is set already + should_trap = Signal(reset_less=True) + comb += should_trap.eq((trap_bits & to).any() | traptype.any()) # TODO: some #defines for the bits n stuff. - with m.Switch(op): + with m.Switch(op.insn_type): #### trap #### with m.Case(InternalOp.OP_TRAP): - """ - -- trap instructions (tw, twi, td, tdi) - if or (trapval and insn_to(e_in.insn)) = '1' then - -- generate trap-type program interrupt - exception := '1'; - ctrl_tmp.irq_nia <= std_logic_vector(to_unsigned(16#700#, 64)); - ctrl_tmp.srr1 <= msr_copy(ctrl.msr); - -- set bit 46 to say trap occurred - ctrl_tmp.srr1(63 - 46) <= '1'; - """ + # trap instructions (tw, twi, td, tdi) with m.If(should_trap): - comb += self.o.nia.data.eq(0x700) # trap address - comb += self.o.nia.ok.eq(1) - comb += self.o.srr1.data.eq(self.i.msr) # old MSR - comb += self.o.srr1.data[63-46].eq(1) # XXX which bit? - comb += self.o.srr1.ok.eq(1) - comb += self.o.srr0.data.eq(self.i.cia) # old PC - comb += self.o.srr0.ok.eq(1) - - # move to SPR - with m.Case(InternalOp.OP_MTMSR): - # TODO: some of the bits need zeroing? - """ - if e_in.insn(16) = '1' then <-- this is X-form field "L". - -- just update EE and RI - ctrl_tmp.msr(MSR_EE) <= c_in(MSR_EE); - ctrl_tmp.msr(MSR_RI) <= c_in(MSR_RI); - else - -- Architecture says to leave out bits 3 (HV), 51 (ME) - -- and 63 (LE) (IBM bit numbering) - ctrl_tmp.msr(63 downto 61) <= c_in(63 downto 61); - ctrl_tmp.msr(59 downto 13) <= c_in(59 downto 13); - ctrl_tmp.msr(11 downto 1) <= c_in(11 downto 1); - if c_in(MSR_PR) = '1' then - ctrl_tmp.msr(MSR_EE) <= '1'; - ctrl_tmp.msr(MSR_IR) <= '1'; - ctrl_tmp.msr(MSR_DR) <= '1'; - """ - # TODO translate this: - # L = self.fields.FormX[0:-1] - # if e_in.insn(16) = '1' then <-- this is X-form field "L". - # -- just update EE and RI - # ctrl_tmp.msr(MSR_EE) <= c_in(MSR_EE); - # ctrl_tmp.msr(MSR_RI) <= c_in(MSR_RI); + # generate trap-type program interrupt + self.trap(m, trapaddr<<4, cia_i) + with m.If(traptype == 0): + # say trap occurred (see 3.0B Book III 7.5.9) + comb += srr1_o.data[PI.TRAP].eq(1) + with m.If(traptype & TT_PRIV): + comb += srr1_o.data[PI.PRIV].eq(1) + with m.If(traptype & TT_FP): + comb += srr1_o.data[PI.FP].eq(1) + with m.If(traptype & TT_ADDR): + comb += srr1_o.data[PI.ADR].eq(1) + with m.If(traptype & TT_ILLEG): + comb += srr1_o.data[PI.ILLEG].eq(1) + + # move to MSR + with m.Case(InternalOp.OP_MTMSRD): + L = self.fields.FormX.L[0:-1] # X-Form field L + with m.If(L): + # just update EE and RI + comb += msr_o.data[MSR.EE].eq(a_i[MSR.EE]) + comb += msr_o.data[MSR.RI].eq(a_i[MSR.RI]) with m.Else(): + # Architecture says to leave out bits 3 (HV), 51 (ME) + # and 63 (LE) (IBM bit numbering) for stt, end in [(1,12), (13, 60), (61, 64)]: - comb += self.o.msr.data[stt:end].eq(a[stt:end]) - with m.If(a[MSR_PR]): - self.o.msr[MSR_EE].eq(1) - self.o.msr[MSR_IR].eq(1) - self.o.msr[MSR_DR].eq(1) - comb += self.o.msr.ok.eq(1) - - # move from SPR + comb += msr_o.data[stt:end].eq(a_i[stt:end]) + msr_check_pr(m, msr_o.data) + comb += msr_o.ok.eq(1) + + # move from MSR with m.Case(InternalOp.OP_MFMSR): # TODO: some of the bits need zeroing? apparently not - """ - when OP_MFMSR => - result := ctrl.msr; - result_en := '1'; - """ - comb += self.o.o.data.eq(self.i.msr) - comb += self.o.o.ok.eq(1) + comb += o.data.eq(msr_i) + comb += o.ok.eq(1) with m.Case(InternalOp.OP_RFID): - """ - # XXX f_out.virt_mode <= b_in(MSR_IR) or b_in(MSR_PR); - # XXX f_out.priv_mode <= not b_in(MSR_PR); - f_out.redirect_nia <= a_in(63 downto 2) & "00"; -- srr0 - -- Can't use msr_copy here because the partial function MSR - -- bits should be left unchanged, not zeroed. - ctrl_tmp.msr(63 downto 31) <= b_in(63 downto 31); - ctrl_tmp.msr(26 downto 22) <= b_in(26 downto 22); - ctrl_tmp.msr(15 downto 0) <= b_in(15 downto 0); - if b_in(MSR_PR) = '1' then - ctrl_tmp.msr(MSR_EE) <= '1'; - ctrl_tmp.msr(MSR_IR) <= '1'; - ctrl_tmp.msr(MSR_DR) <= '1'; - end if; - """ - # TODO translate this, import and use br_ext from branch stage - # f_out.redirect_nia <= a_in(63 downto 2) & "00"; -- srr0 - for stt, end in [(0,16), (22, 27), (31, 64)]: - comb += self.o.msr.data[stt:end].eq(a[stt:end]) - with m.If(a[MSR_PR]): - self.o.msr[MSR_EE].eq(1) - self.o.msr[MSR_IR].eq(1) - self.o.msr[MSR_DR].eq(1) - comb += self.o.msr.ok.eq(1) - - # TODO + # XXX f_out.virt_mode <= b_in(MSR.IR) or b_in(MSR.PR); + # XXX f_out.priv_mode <= not b_in(MSR.PR); + + # return addr was in srr0 + comb += nia_o.data.eq(br_ext(srr0_i[2:])) + comb += nia_o.ok.eq(1) + # MSR was in srr1 + comb += msr_copy(msr_o.data, srr1_i, zero_me=False) # don't zero + msr_check_pr(m, msr_o.data) + + # hypervisor stuff + comb += msr_o.data[MSR.HV].eq(msr_i[MSR.HV] & srr1_i[MSR.HV]) + comb += msr_o.data[MSR.ME].eq((msr_i[MSR.HV] & srr1_i[MSR.HV]) | + (~msr_i[MSR.HV] & srr1_i[MSR.HV])) + # don't understand but it's in the spec + with m.If((msr_i[63-31:63-29] != Const(0b010, 3)) | + (srr1_i[63-31:63-29] != Const(0b000, 3))): + comb += msr_o.data[63-31:63-29].eq(srr1_i[63-31:63-29]) + with m.Else(): + comb += msr_o.data[63-31:63-29].eq(msr_i[63-31:63-29]) + comb += msr_o.ok.eq(1) + + # OP_SC with m.Case(InternalOp.OP_SC): - """ # TODO: scv must generate illegal instruction. this is # the decoder's job, not ours, here. - ctrl_tmp.irq_nia <= std_logic_vector(to_unsigned(16#C00#, 64)); - ctrl_tmp.srr1 <= msr_copy(ctrl.msr); - """ - comb += self.o.nia.eq(0xC00) # trap address - comb += self.o.nia.ok.eq(1) - # TODO translate this line: ctrl_tmp.srr1 <= msr_copy(ctrl.msr); - comb += self.o.srr1.ok.eq(1) + + # jump to the trap address, return at cia+4 + self.trap(m, 0xc00, cia_i+4) # TODO (later) #with m.Case(InternalOp.OP_ADDPCIS):