X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fsoc%2Ffu%2Ftrap%2Fpipe_data.py;h=de55cf2e57072bf35623581603a60373d459e4d9;hb=0046884fcff53877a6cbfa322c0a86f6a6a17361;hp=99fe070943a6211eeceb893ad04d1bf1c9f19bf0;hpb=022c968392e979c6d8408600869a89bbf605aabb;p=soc.git

diff --git a/src/soc/fu/trap/pipe_data.py b/src/soc/fu/trap/pipe_data.py
index 99fe0709..de55cf2e 100644
--- a/src/soc/fu/trap/pipe_data.py
+++ b/src/soc/fu/trap/pipe_data.py
@@ -5,29 +5,29 @@ from soc.fu.trap.trap_input_record import CompTrapOpSubset
 class TrapInputData(IntegerData):
     regspec = [('INT', 'ra', '0:63'),  # RA
                ('INT', 'rb', '0:63'),  # RB/immediate
-               ('FAST', 'spr1', '0:63'), # SRR0
-               ('FAST', 'cia', '0:63'),  # Program counter (current)
-               ('FAST', 'msr', '0:63')]  # MSR
+               ('FAST', 'fast1', '0:63'), # SRR0
+               ('FAST', 'fast2', '0:63'), # SRR1
+               ] 
     def __init__(self, pspec):
         super().__init__(pspec, False)
         # convenience
-        self.srr0, self.a, self.b = self.spr1, self.ra, self.rb
+        self.srr0, self.srr1 = self.fast1, self.fast2
+        self.a, self.b = self.ra, self.rb
 
 
 class TrapOutputData(IntegerData):
     regspec = [('INT', 'o', '0:63'),     # RA
-               ('FAST', 'spr1', '0:63'), # SRR0 SPR
-               ('FAST', 'spr2', '0:63'), # SRR1 SPR
+               ('FAST', 'fast1', '0:63'), # SRR0 SPR
+               ('FAST', 'fast2', '0:63'), # SRR1 SPR
                ('FAST', 'nia', '0:63'),  # NIA (Next PC)
                ('FAST', 'msr', '0:63')]  # MSR
     def __init__(self, pspec):
         super().__init__(pspec, True)
         # convenience
-        self.srr0, self.srr1 = self.spr1, self.spr2
+        self.srr0, self.srr1 = self.fast1, self.fast2
 
 
 
-# TODO: replace CompALUOpSubset with CompTrapOpSubset
 class TrapPipeSpec(CommonPipeSpec):
     regspec = (TrapInputData.regspec, TrapOutputData.regspec)
     opsubsetkls = CompTrapOpSubset