X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fsoc%2Finterrupts%2Fxics.py;h=ede33a1b03913307f33ce8080652d315c0403ce9;hb=5963eef6679f6833b6b8f854868d90480e3753b2;hp=1b6b95fd26505020035e9cd73ad27b5d6495804a;hpb=9d4e6cfeaf200bd4870989242ae9f6bede65b710;p=soc.git

diff --git a/src/soc/interrupts/xics.py b/src/soc/interrupts/xics.py
index 1b6b95fd..ede33a1b 100644
--- a/src/soc/interrupts/xics.py
+++ b/src/soc/interrupts/xics.py
@@ -78,7 +78,7 @@ class XICS_ICP(Elaboratable):
         spec.addr_wid = 30
         spec.mask_wid = 4
         spec.reg_wid = 32
-        self.bus = Record(make_wb_layout(spec), name="icp_wb")
+        self.bus = Record(make_wb_layout(spec, cti=False), name="icp_wb")
         self.ics_i = ICS2ICP("ics_i")
         self.core_irq_o = Signal()
 
@@ -93,8 +93,9 @@ class XICS_ICP(Elaboratable):
         # We delay core_irq_out by a cycle to help with timing
         sync += self.core_irq_o.eq(r.irq)
 
-        comb += self.bus.dat_r.eq(r.wb_rd_data)
-        comb += self.bus.ack.eq(r.wb_ack)
+        comb += self.bus.ack.eq(r.wb_ack & self.bus.cyc)
+        with m.If(self.bus.ack):
+            comb += self.bus.dat_r.eq(r.wb_rd_data)
 
         v = RegInternal()
         xirr_accept_rd = Signal()
@@ -135,7 +136,7 @@ class XICS_ICP(Elaboratable):
                             #report "ICP XIRR UNSUPPORTED write ! sel=" & \
                             #           to_hstring(self.bus.sel);
                             pass
-                    with m.Case(MFRR ):
+                    with m.Case(MFRR):
                         comb += v.mfrr.eq(be_in[24:32])
                         with m.If(self.bus.sel == 0xf): #  # 4 byte
                             # report "ICP MFRR write word:" & to_hstring(be_in);
@@ -154,7 +155,7 @@ class XICS_ICP(Elaboratable):
                 with m.Switch(self.bus.adr[:6]):
                     with m.Case(XIRR_POLL):
                         # report "ICP XIRR_POLL read";
-                        comb += be_out.eq(r.xisr & r.cppr)
+                        comb += be_out.eq(Cat(r.xisr, r.cppr))
                     with m.Case(XIRR):
                         # report "ICP XIRR read";
                         comb += be_out.eq(Cat(r.xisr, r.cppr))
@@ -162,7 +163,7 @@ class XICS_ICP(Elaboratable):
                             comb += xirr_accept_rd.eq(1)
                     with m.Case(MFRR):
                         # report "ICP MFRR read";
-                        comb += be_out.eq(r.mfrr)
+                        comb += be_out[24:32].eq(r.mfrr)
 
         comb += pending_priority.eq(0xff)
         comb += v.xisr.eq(0x0)
@@ -175,7 +176,7 @@ class XICS_ICP(Elaboratable):
 
         # Check MFRR
         with m.If(r.mfrr < pending_priority):
-            comb += v.xisr.eq(Const(0x2)) # special XICS MFRR IRQ source number
+            comb += v.xisr.eq(Const(0x2, 24)) # special XICS MFRR IRQ src num
             comb += min_pri.eq(r.mfrr)
         with m.Else():
             comb += min_pri.eq(pending_priority)
@@ -191,11 +192,11 @@ class XICS_ICP(Elaboratable):
         comb += v.wb_rd_data.eq(bswap(be_out))
 
         # check if the core needs an interrupt notification (or clearing)
-        comb += v.irq.eq(min_pri < v.cppr)
-        with m.If(v.irq):
+        with m.If(min_pri < v.cppr):
             with m.If(~r.irq):
                 #report "IRQ set";
                 pass
+            comb += v.irq.eq(1)
         with m.Elif(r.irq):
             #report "IRQ clr";
             pass
@@ -231,7 +232,7 @@ class XICS_ICS(Elaboratable):
         spec.addr_wid = 30
         spec.mask_wid = 4
         spec.reg_wid = 32
-        self.bus = Record(make_wb_layout(spec), name="ics_wb")
+        self.bus = Record(make_wb_layout(spec, cti=False), name="ics_wb")
 
         self.int_level_i = Signal(SRC_NUM)
         self.icp_o = ICS2ICP("icp_o")