X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fsoc%2Flitex%2Fflorent%2Flibresoc%2Fcore.py;h=3bc76798f64cc170f5672336e17c9169bb774920;hb=0750c1e02fe3655d8b4bf0c81b87879e9aea3192;hp=44202b3b6d89aa3c2fe9f1177e053d4e7bca96a4;hpb=4d4d7dcd00a6d40a297ae7f9a85931a8992293c5;p=soc.git

diff --git a/src/soc/litex/florent/libresoc/core.py b/src/soc/litex/florent/libresoc/core.py
index 44202b3b..3bc76798 100644
--- a/src/soc/litex/florent/libresoc/core.py
+++ b/src/soc/litex/florent/libresoc/core.py
@@ -5,11 +5,11 @@ from migen import ClockSignal, ResetSignal, Signal, Instance, Cat
 from litex.soc.interconnect import wishbone as wb
 from litex.soc.cores.cpu import CPU
 
-from soc.debug.jtag import Pins, dummy_pinset # TODO move to suitable location
+from soc.config.pinouts import get_pinspecs
+from soc.debug.jtag import Pins
 from c4m.nmigen.jtag.tap import IOType
 
 from libresoc.ls180 import io
-from libresoc.ls180io import make_uart, make_gpio
 from litex.build.generic_platform import ConstraintManager
 
 
@@ -50,20 +50,39 @@ def get_field(rec, name):
 def make_jtag_ioconn(res, pin, cpupads, iopads):
     (fn, pin, iotype, pin_name, scan_idx) = pin
     #serial_tx__core__o, serial_rx__pad__i,
+    # special-case sdram_clock
+    if pin == 'clock' and fn == 'sdr':
+        cpu = cpupads['sdram_clock']
+        io = iopads['sdram_clock']
+    else:
+        cpu = cpupads[fn]
+        io = iopads[fn]
     print ("cpupads", cpupads)
     print ("iopads", iopads)
     print ("pin", fn, pin, iotype, pin_name)
-    cpu = cpupads[fn]
-    io = iopads[fn]
     print ("cpu fn", cpu)
     print ("io fn", io)
-    sigs = []
-
     name = "%s_%s" % (fn, pin)
+    print ("name", name)
+    sigs = []
 
     if iotype in (IOType.In, IOType.Out):
-        cpup = getattr(cpu, pin)
-        iop = getattr(io, pin)
+        ps = pin.split("_")
+        if pin == 'clock' and fn == 'sdr':
+            cpup = cpu
+            iop = io
+        elif len(ps) == 2 and ps[-1].isdigit():
+            pin, idx = ps
+            idx = int(idx)
+            cpup = getattr(cpu, pin)[idx]
+            iop = getattr(io, pin)[idx]
+        elif pin.isdigit():
+            idx = int(pin)
+            cpup = cpu[idx]
+            iop = io[idx]
+        else:
+            cpup = getattr(cpu, pin)
+            iop = getattr(io, pin)
 
     if iotype == IOType.Out:
         # output from the pad is routed through C4M JTAG and so
@@ -77,7 +96,7 @@ def make_jtag_ioconn(res, pin, cpupads, iopads):
 
     elif iotype == IOType.InTriOut:
         if fn == 'gpio': # sigh decode GPIO special-case
-            idx = int(pin[4:])
+            idx = int(pin[1:])
         else:
             idx = 0
         cpup, iop = get_field(cpu, "i")[idx], get_field(io, "i")[idx]
@@ -129,7 +148,10 @@ class LibreSoC(CPU):
         self.platform     = platform
         self.variant      = variant
         self.reset        = Signal()
-        self.interrupt    = Signal(16)
+        irq_en = "noirq" not in variant
+
+        if irq_en:
+            self.interrupt    = Signal(16)
 
         if variant == "standard32":
             self.data_width           = 32
@@ -181,11 +203,12 @@ class LibreSoC(CPU):
             o_memerr_o         = Signal(),   # not connected
             o_pc_o             = Signal(64), # not connected
 
-            # interrupts
-            i_int_level_i      = self.interrupt,
-
         )
 
+        if irq_en:
+            # interrupts
+            self.cpu_params['i_int_level_i'] = self.interrupt
+
         if jtag_en:
             self.cpu_params.update(dict(
                 # JTAG Debug bus
@@ -229,11 +252,38 @@ class LibreSoC(CPU):
             self.pad_cm = ConstraintManager(self.padresources, [])
             self.cpupads = {}
             iopads = {}
-            for (periph, num) in [('uart', 0), ('gpio', 0), ('i2c', 0)]:
-                self.cpupads[periph] = platform.request(periph, num)
-                iopads[periph] = self.pad_cm.request(periph, num)
-
-            p = Pins(dummy_pinset())
+            litexmap = {}
+            subset = {'uart', 'mtwi', 'eint', 'gpio', 'mspi0', 'mspi1',
+                      'pwm', 'sd0', 'sdr'}
+            for periph in subset:
+                origperiph = periph
+                num = None
+                if periph[-1].isdigit():
+                    periph, num = periph[:-1], int(periph[-1])
+                print ("periph request", periph, num)
+                if periph == 'mspi':
+                    if num == 0:
+                        periph, num = 'spimaster', None
+                    else:
+                        periph, num = 'spisdcard', None
+                elif periph == 'sdr':
+                    periph = 'sdram'
+                elif periph == 'mtwi':
+                    periph = 'i2c'
+                elif periph == 'sd':
+                    periph, num = 'sdcard', None
+                litexmap[origperiph] = (periph, num)
+                self.cpupads[origperiph] = platform.request(periph, num)
+                iopads[origperiph] = self.pad_cm.request(periph, num)
+                if periph == 'sdram':
+                    # special-case sdram clock
+                    ck = platform.request("sdram_clock")
+                    self.cpupads['sdram_clock'] = ck
+                    ck = self.pad_cm.request("sdram_clock")
+                    iopads['sdram_clock'] = ck
+
+            pinset = get_pinspecs(subset=subset)
+            p = Pins(pinset)
             for pin in list(p):
                 make_jtag_ioconn(self.cpu_params, pin, self.cpupads, iopads)