X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fsoc%2Fsimple%2Fcore.py;h=e9eb1a189a29c6036868bd049fe75b6b3f9ae405;hb=157669066b9990ca430f49293bcd97f9ae51890d;hp=84555c37b5cf83ec0c3b099f15fa6d54090cd8aa;hpb=cb49428fe0347ec2a939f884e8fe3e5d2b1eae21;p=soc.git

diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py
index 84555c37..e9eb1a18 100644
--- a/src/soc/simple/core.py
+++ b/src/soc/simple/core.py
@@ -117,7 +117,7 @@ class NonProductionCore(Elaboratable):
             self.sv_pred_dm = Signal() # TODO: SIMD width
 
         # issue/valid/busy signalling
-        self.ivalid_i = Signal(reset_less=True) # instruction is valid
+        self.ii_valid = Signal(reset_less=True) # instruction is valid
         self.issue_i = Signal(reset_less=True)
         self.busy_o = Signal(name="corebusy_o", reset_less=True)
 
@@ -226,7 +226,7 @@ class NonProductionCore(Elaboratable):
             sync += counter.eq(counter - 1)
             comb += self.busy_o.eq(1)
 
-        with m.If(self.ivalid_i): # run only when valid
+        with m.If(self.ii_valid): # run only when valid
             with m.Switch(self.e.do.insn_type):
                 # check for ATTN: halt if true
                 with m.Case(MicrOp.OP_ATTN):