X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fsoc%2Fsimple%2Fissuer.py;h=156fce3cdf79ddc786804e6342a49533b12f3397;hb=8c0a56c349b0d5650026e0ce9031272104cdc39a;hp=1dedcdba05b832c651ab3c7d5ff81fcad8494492;hpb=b9abbdbd8d08e6e3bfdbef8400c5554365a68826;p=soc.git diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py index 1dedcdba..156fce3c 100644 --- a/src/soc/simple/issuer.py +++ b/src/soc/simple/issuer.py @@ -176,12 +176,18 @@ class TestIssuerBase(Elaboratable): self.allow_overlap = (hasattr(pspec, "allow_overlap") and (pspec.allow_overlap == True)) + # and get the core domain + self.core_domain = "coresync" + if (hasattr(pspec, "core_domain") and + isinstance(pspec.core_domain, str)): + self.core_domain = pspec.core_domain + # JTAG interface. add this right at the start because if it's # added it *modifies* the pspec, by adding enable/disable signals # for parts of the rest of the core self.jtag_en = hasattr(pspec, "debug") and pspec.debug == 'jtag' - self.dbg_domain = "sync" # sigh "dbgsunc" too problematic - # self.dbg_domain = "dbgsync" # domain for DMI/JTAG clock + #self.dbg_domain = "sync" # sigh "dbgsunc" too problematic + self.dbg_domain = "dbgsync" # domain for DMI/JTAG clock if self.jtag_en: # XXX MUST keep this up-to-date with litex, and # soc-cocotb-sim, and err.. all needs sorting out, argh @@ -229,7 +235,7 @@ class TestIssuerBase(Elaboratable): # main instruction core. suitable for prototyping / demo only self.core = core = NonProductionCore(pspec) - self.core_rst = ResetSignal("coresync") + self.core_rst = ResetSignal(self.core_domain) # instruction decoder. goes into Trap Record #pdecode = create_pdecode() @@ -255,6 +261,7 @@ class TestIssuerBase(Elaboratable): # DMI interface self.dbg = CoreDebug() + self.dbg_rst_i = Signal(reset_less=True) # instruction go/monitor self.pc_o = Signal(64, reset_less=True) @@ -310,7 +317,7 @@ class TestIssuerBase(Elaboratable): # but NOT its reset signal. to cope with this, set every single # submodule explicitly in coresync domain, debug and JTAG # in their own one but using *external* reset. - csd = DomainRenamer("coresync") + csd = DomainRenamer(self.core_domain) dbd = DomainRenamer(self.dbg_domain) m.submodules.core = core = csd(self.core) @@ -363,8 +370,10 @@ class TestIssuerBase(Elaboratable): # clock delay power-on reset cd_por = ClockDomain(reset_less=True) cd_sync = ClockDomain() - core_sync = ClockDomain("coresync") - m.domains += cd_por, cd_sync, core_sync + m.domains += cd_por, cd_sync + core_sync = ClockDomain(self.core_domain) + if self.core_domain != "sync": + m.domains += core_sync if self.dbg_domain != "sync": dbg_sync = ClockDomain(self.dbg_domain) m.domains += dbg_sync @@ -376,14 +385,18 @@ class TestIssuerBase(Elaboratable): comb += cd_por.clk.eq(ClockSignal()) # power-on reset delay - core_rst = ResetSignal("coresync") - comb += ti_rst.eq(delay != 0 | dbg.core_rst_o | ResetSignal()) - comb += core_rst.eq(ti_rst) + core_rst = ResetSignal(self.core_domain) + if self.core_domain != "sync": + comb += ti_rst.eq(delay != 0 | dbg.core_rst_o | ResetSignal()) + comb += core_rst.eq(ti_rst) + else: + with m.If(delay != 0 | dbg.core_rst_o): + comb += core_rst.eq(1) - # debug clock is same as coresync, but reset is *main external* + # connect external reset signal to DMI Reset if self.dbg_domain != "sync": dbg_rst = ResetSignal(self.dbg_domain) - comb += dbg_rst.eq(ResetSignal()) + comb += dbg_rst.eq(self.dbg_rst_i) # busy/halted signals from core core_busy_o = ~core.p.o_ready | core.n.o_data.busy_o # core is busy @@ -512,6 +525,15 @@ class TestIssuerBase(Elaboratable): with m.If(core_rst): m.d.sync += self.cur_state.eq(0) + # check halted condition: requested PC to execute matches DMI stop addr + # and immediately stop. address of 0xffff_ffff_ffff_ffff can never + # match + halted = Signal() + comb += halted.eq(dbg.stop_addr_o == dbg.state.pc) + with m.If(halted): + comb += dbg.core_stopped_i.eq(1) + comb += dbg.terminate_i.eq(1) + # PC and instruction from I-Memory comb += self.pc_o.eq(cur_state.pc) self.pc_changed = Signal() # note write to PC @@ -697,9 +719,10 @@ class FetchFSM(ControlBase): # waiting (zzz) with m.State("IDLE"): - with m.If(~dbg.stopping_o & ~fetch_failed): + with m.If(~dbg.stopping_o & ~fetch_failed & ~dbg.core_stop_o): comb += fetch_pc_o_ready.eq(1) - with m.If(fetch_pc_i_valid & ~pdecode2.instr_fault): + with m.If(fetch_pc_i_valid & ~pdecode2.instr_fault + & ~dbg.core_stop_o): # instruction allowed to go: start by reading the PC # capture the PC and also drop it into Insn Memory # we have joined a pair of combinatorial memory @@ -733,7 +756,12 @@ class FetchFSM(ControlBase): # not busy (or fetch failed!): instruction fetched # when fetch failed, the instruction gets ignored # by the decoder - insn = get_insn(self.imem.f_instr_o, cur_state.pc) + if hasattr(core, "icache"): + # blech, icache returns actual instruction + insn = self.imem.f_instr_o + else: + # but these return raw memory + insn = get_insn(self.imem.f_instr_o, cur_state.pc) if self.svp64_en: svp64 = self.svp64 # decode the SVP64 prefix, if any @@ -1387,7 +1415,8 @@ class TestIssuerInternal(TestIssuerBase): nia = Signal(64) # connect up debug signals - comb += dbg.terminate_i.eq(core.o.core_terminate_o) + with m.If(core.o.core_terminate_o): + comb += dbg.terminate_i.eq(1) # pass the prefix mode from Fetch to Issue, so the latter can loop # on VL==0 @@ -1475,6 +1504,8 @@ class TestIssuer(Elaboratable): #self.ti = TestIssuerInternalInOrder(pspec) self.pll = DummyPLL(instance=True) + self.dbg_rst_i = Signal(reset_less=True) + # PLL direct clock or not self.pll_en = hasattr(pspec, "use_pll") and pspec.use_pll if self.pll_en: @@ -1521,23 +1552,24 @@ class TestIssuer(Elaboratable): # internal clock is set to selector clock-out. has the side-effect of # running TestIssuer at this speed (see DomainRenamer("intclk") above) # debug clock runs at coresync internal clock - cd_coresync = ClockDomain("coresync") - #m.domains += cd_coresync if self.ti.dbg_domain != 'sync': cd_dbgsync = ClockDomain("dbgsync") - #m.domains += cd_dbgsync - intclk = ClockSignal("coresync") + intclk = ClockSignal(self.ti.core_domain) dbgclk = ClockSignal(self.ti.dbg_domain) # XXX BYPASS PLL XXX # XXX BYPASS PLL XXX # XXX BYPASS PLL XXX if self.pll_en: comb += intclk.eq(self.ref_clk) + assert self.ti.core_domain != 'sync', \ + "cannot set core_domain to sync and use pll at the same time" else: - comb += intclk.eq(ClockSignal()) + if self.ti.core_domain != 'sync': + comb += intclk.eq(ClockSignal()) if self.ti.dbg_domain != 'sync': dbgclk = ClockSignal(self.ti.dbg_domain) comb += dbgclk.eq(intclk) + comb += self.ti.dbg_rst_i.eq(self.dbg_rst_i) return m