X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fsoc%2Fsimple%2Fissuer.py;h=6da1610ce25a487d4014287d8dfb76ae12b51122;hb=67f14bcb5cd27a55e1ea1b894e0a9ba7686ff48f;hp=ffb7dc9710a21152e88f7d0c98113b4929b44933;hpb=b54612199531fcf960722e9e8c03f3b242f551f7;p=soc.git

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index ffb7dc97..6da1610c 100644
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -713,13 +713,15 @@ class FetchFSM(ControlBase):
         # set priv / virt mode on I-Cache, sigh
         if isinstance(self.imem, ICache):
             comb += self.imem.i_in.priv_mode.eq(~msr[MSR.PR])
-            comb += self.imem.i_in.virt_mode.eq(msr[MSR.DR])
+            comb += self.imem.i_in.virt_mode.eq(msr[MSR.IR]) # Instr. Redir (VM)
 
         with m.FSM(name='fetch_fsm'):
 
             # waiting (zzz)
             with m.State("IDLE"):
-                with m.If(~dbg.stopping_o & ~fetch_failed & ~dbg.core_stop_o):
+                # fetch allowed if not failed and stopped but not stepping
+                # (see dmi.py for how core_stop_o is generated)
+                with m.If(~fetch_failed & ~dbg.core_stop_o):
                     comb += fetch_pc_o_ready.eq(1)
                 with m.If(fetch_pc_i_valid & ~pdecode2.instr_fault
                           & ~dbg.core_stop_o):
@@ -739,10 +741,11 @@ class FetchFSM(ControlBase):
 
             # dummy pause to find out why simulation is not keeping up
             with m.State("INSN_READ"):
-                if self.allow_overlap:
-                    stopping = dbg.stopping_o
-                else:
-                    stopping = Const(0)
+                # when using "single-step" mode, checking dbg.stopping_o
+                # prevents progress.  allow fetch to proceed once started
+                stopping = Const(0)
+                #if self.allow_overlap:
+                #    stopping = dbg.stopping_o
                 with m.If(stopping):
                     # stopping: jump back to idle
                     m.next = "IDLE"
@@ -1094,10 +1097,11 @@ class TestIssuerInternal(TestIssuerBase):
 
             # wait for an instruction to arrive from Fetch
             with m.State("INSN_WAIT"):
-                if self.allow_overlap:
-                    stopping = dbg.stopping_o
-                else:
-                    stopping = Const(0)
+                # when using "single-step" mode, checking dbg.stopping_o
+                # prevents progress.  allow issue to proceed once started
+                stopping = Const(0)
+                #if self.allow_overlap:
+                #    stopping = dbg.stopping_o
                 with m.If(stopping):
                     # stopping: jump back to idle
                     m.next = "ISSUE_START"
@@ -1232,10 +1236,11 @@ class TestIssuerInternal(TestIssuerBase):
 
             # handshake with execution FSM, move to "wait" once acknowledged
             with m.State("INSN_EXECUTE"):
-                if self.allow_overlap:
-                    stopping = dbg.stopping_o
-                else:
-                    stopping = Const(0)
+                # when using "single-step" mode, checking dbg.stopping_o
+                # prevents progress.  allow execute to proceed once started
+                stopping = Const(0)
+                #if self.allow_overlap:
+                #    stopping = dbg.stopping_o
                 with m.If(stopping):
                     # stopping: jump back to idle
                     m.next = "ISSUE_START"