X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fsoc%2Fsimple%2Fissuer.py;h=9b7ed9c59d4f23a4ecfe37ef9e48137c5d1e98bb;hb=b3a125fac4792231aac25b022028401b7ba6ae6c;hp=c8dac1475873a21ec38cd85c6ea3b4e28b6f8bc7;hpb=dbb140cd79611e59071d40416cd975f0f524faf2;p=soc.git

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index c8dac147..9b7ed9c5 100644
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -16,7 +16,7 @@ improved.
 """
 
 from nmigen import (Elaboratable, Module, Signal, ClockSignal, ResetSignal,
-                    ClockDomain, DomainRenamer, Mux)
+                    ClockDomain, DomainRenamer, Mux, Const, Repl)
 from nmigen.cli import rtlil
 from nmigen.cli import main
 import sys
@@ -30,15 +30,18 @@ from soc.regfile.regfiles import StateRegs, FastRegs
 from soc.simple.core import NonProductionCore
 from soc.config.test.test_loadstore import TestMemPspec
 from soc.config.ifetch import ConfigFetchUnit
-from soc.decoder.power_enums import MicrOp
+from soc.decoder.power_enums import (MicrOp, SVP64PredInt, SVP64PredCR,
+                                     SVP64PredMode)
 from soc.debug.dmi import CoreDebug, DMIInterface
 from soc.debug.jtag import JTAG
 from soc.config.pinouts import get_pinspecs
 from soc.config.state import CoreState
 from soc.interrupts.xics import XICS_ICP, XICS_ICS
 from soc.bus.simple_gpio import SimpleGPIO
+from soc.bus.SPBlock512W64B8W import SPBlock512W64B8W
 from soc.clock.select import ClockSelect
 from soc.clock.dummypll import DummyPLL
+from soc.sv.svstate import SVSTATERec
 
 
 from nmutil.util import rising_edge
@@ -50,14 +53,115 @@ def get_insn(f_instr_o, pc):
         # 64-bit: bit 2 of pc decides which word to select
         return f_instr_o.word_select(pc[2], 32)
 
+# gets state input or reads from state regfile
+def state_get(m, state_i, name, regfile, regnum):
+    comb = m.d.comb
+    sync = m.d.sync
+    # read the PC
+    res = Signal(64, reset_less=True, name=name)
+    res_ok_delay = Signal(name="%s_ok_delay" % name)
+    sync += res_ok_delay.eq(~state_i.ok)
+    with m.If(state_i.ok):
+        # incoming override (start from pc_i)
+        comb += res.eq(state_i.data)
+    with m.Else():
+        # otherwise read StateRegs regfile for PC...
+        comb += regfile.ren.eq(1<<regnum)
+    # ... but on a 1-clock delay
+    with m.If(res_ok_delay):
+        comb += res.eq(regfile.data_o)
+    return res
+
+def get_predint(m, mask, name):
+    """decode SVP64 predicate integer mask field to reg number and invert
+    this is identical to the equivalent function in ISACaller except that
+    it doesn't read the INT directly, it just decodes "what needs to be done"
+    i.e. which INT reg, whether it is shifted and whether it is bit-inverted.
+
+    * all1s is set to indicate that no mask is to be applied.
+    * regread indicates the GPR register number to be read
+    * invert is set to indicate that the register value is to be inverted
+    * unary indicates that the contents of the register is to be shifted 1<<r3
+    """
+    comb = m.d.comb
+    regread = Signal(5, name=name+"regread")
+    invert = Signal(name=name+"invert")
+    unary = Signal(name=name+"unary")
+    all1s = Signal(name=name+"all1s")
+    with m.Switch(mask):
+        with m.Case(SVP64PredInt.ALWAYS.value):
+            comb += all1s.eq(1)      # use 0b1111 (all ones)
+        with m.Case(SVP64PredInt.R3_UNARY.value):
+            comb += regread.eq(3)
+            comb += unary.eq(1)        # 1<<r3 - shift r3 (single bit)
+        with m.Case(SVP64PredInt.R3.value):
+            comb += regread.eq(3)
+        with m.Case(SVP64PredInt.R3_N.value):
+            comb += regread.eq(3)
+            comb += invert.eq(1)
+        with m.Case(SVP64PredInt.R10.value):
+            comb += regread.eq(10)
+        with m.Case(SVP64PredInt.R10_N.value):
+            comb += regread.eq(10)
+            comb += invert.eq(1)
+        with m.Case(SVP64PredInt.R30.value):
+            comb += regread.eq(30)
+        with m.Case(SVP64PredInt.R30_N.value):
+            comb += regread.eq(30)
+            comb += invert.eq(1)
+    return regread, invert, unary, all1s
+
+def get_predcr(m, mask, name):
+    """decode SVP64 predicate CR to reg number field and invert status
+    this is identical to _get_predcr in ISACaller
+    """
+    comb = m.d.comb
+    idx = Signal(2, name=name+"idx")
+    invert = Signal(name=name+"crinvert")
+    with m.Switch(mask):
+        with m.Case(SVP64PredCR.LT.value):
+            comb += idx.eq(0)
+            comb += invert.eq(1)
+        with m.Case(SVP64PredCR.GE.value):
+            comb += idx.eq(0)
+            comb += invert.eq(0)
+        with m.Case(SVP64PredCR.GT.value):
+            comb += idx.eq(1)
+            comb += invert.eq(1)
+        with m.Case(SVP64PredCR.LE.value):
+            comb += idx.eq(1)
+            comb += invert.eq(0)
+        with m.Case(SVP64PredCR.EQ.value):
+            comb += idx.eq(2)
+            comb += invert.eq(1)
+        with m.Case(SVP64PredCR.NE.value):
+            comb += idx.eq(1)
+            comb += invert.eq(0)
+        with m.Case(SVP64PredCR.SO.value):
+            comb += idx.eq(3)
+            comb += invert.eq(1)
+        with m.Case(SVP64PredCR.NS.value):
+            comb += idx.eq(3)
+            comb += invert.eq(0)
+    return idx, invert
+
 
 class TestIssuerInternal(Elaboratable):
     """TestIssuer - reads instructions from TestMemory and issues them
 
-    efficiency and speed is not the main goal here: functional correctness is.
+    efficiency and speed is not the main goal here: functional correctness
+    and code clarity is.  optimisations (which almost 100% interfere with
+    easy understanding) come later.
     """
     def __init__(self, pspec):
 
+        # test is SVP64 is to be enabled
+        self.svp64_en = hasattr(pspec, "svp64") and (pspec.svp64 == True)
+
+        # and if regfiles are reduced
+        self.regreduce_en = (hasattr(pspec, "regreduce") and
+                                            (pspec.regreduce == True))
+
         # JTAG interface.  add this right at the start because if it's
         # added it *modifies* the pspec, by adding enable/disable signals
         # for parts of the rest of the core
@@ -73,6 +177,18 @@ class TestIssuerInternal(Elaboratable):
             # honestly probably not.
             pspec.wb_icache_en = self.jtag.wb_icache_en
             pspec.wb_dcache_en = self.jtag.wb_dcache_en
+            self.wb_sram_en = self.jtag.wb_sram_en
+        else:
+            self.wb_sram_en = Const(1)
+
+        # add 4k sram blocks?
+        self.sram4x4k = (hasattr(pspec, "sram4x4kblock") and
+                         pspec.sram4x4kblock == True)
+        if self.sram4x4k:
+            self.sram4k = []
+            for i in range(4):
+                self.sram4k.append(SPBlock512W64B8W(name="sram4k_%d" % i,
+                                                    features={'err'}))
 
         # add interrupt controller?
         self.xics = hasattr(pspec, "xics") and pspec.xics == True
@@ -87,21 +203,21 @@ class TestIssuerInternal(Elaboratable):
             self.simple_gpio = SimpleGPIO()
             self.gpio_o = self.simple_gpio.gpio_o
 
-        # main instruction core25
+        # main instruction core.  suitable for prototyping / demo only
         self.core = core = NonProductionCore(pspec)
 
         # instruction decoder.  goes into Trap Record
         pdecode = create_pdecode()
-        self.cur_state = CoreState("cur") # current state (MSR/PC/EINT/SVSTATE)
+        self.cur_state = CoreState("cur") # current state (MSR/PC/SVSTATE)
         self.pdecode2 = PowerDecode2(pdecode, state=self.cur_state,
-                                     opkls=IssuerDecode2ToOperand)
-        self.svp64 = SVP64PrefixDecoder() # for decoding SVP64 prefix
+                                     opkls=IssuerDecode2ToOperand,
+                                     svp64_en=self.svp64_en,
+                                     regreduce_en=self.regreduce_en)
+        if self.svp64_en:
+            self.svp64 = SVP64PrefixDecoder() # for decoding SVP64 prefix
 
         # Test Instruction memory
         self.imem = ConfigFetchUnit(pspec).fu
-        # one-row cache of instruction read
-        self.iline = Signal(64) # one instruction line
-        self.iprev_adr = Signal(64) # previous address: if different, do read
 
         # DMI interface
         self.dbg = CoreDebug()
@@ -109,7 +225,8 @@ class TestIssuerInternal(Elaboratable):
         # instruction go/monitor
         self.pc_o = Signal(64, reset_less=True)
         self.pc_i = Data(64, "pc_i") # set "ok" to indicate "please change me"
-        self.core_bigendian_i = Signal()
+        self.svstate_i = Data(32, "svstate_i") # ditto
+        self.core_bigendian_i = Signal() # TODO: set based on MSR.LE
         self.busy_o = Signal(reset_less=True)
         self.memerr_o = Signal(reset_less=True)
 
@@ -129,12 +246,496 @@ class TestIssuerInternal(Elaboratable):
         self.cr_r = crrf.r_ports['full_cr_dbg'] # CR read
         self.xer_r = xerrf.r_ports['full_xer'] # XER read
 
+        if self.svp64_en:
+            # for predication
+            self.int_pred = intrf.r_ports['pred'] # INT predicate read
+            self.cr_pred = crrf.r_ports['cr_pred'] # CR predicate read
+
         # hack method of keeping an eye on whether branch/trap set the PC
         self.state_nia = self.core.regs.rf['state'].w_ports['nia']
         self.state_nia.wen.name = 'state_nia_wen'
 
-    def elaborate(self, platform):
-        m = Module()
+        # pulse to synchronize the simulator at instruction end
+        self.insn_done = Signal()
+
+        if self.svp64_en:
+            # store copies of predicate masks
+            self.srcmask = Signal(64)
+            self.dstmask = Signal(64)
+
+    def fetch_fsm(self, m, core, pc, svstate, nia, is_svp64_mode,
+                        fetch_pc_ready_o, fetch_pc_valid_i,
+                        fetch_insn_valid_o, fetch_insn_ready_i):
+        """fetch FSM
+
+        this FSM performs fetch of raw instruction data, partial-decodes
+        it 32-bit at a time to detect SVP64 prefixes, and will optionally
+        read a 2nd 32-bit quantity if that occurs.
+        """
+        comb = m.d.comb
+        sync = m.d.sync
+        pdecode2 = self.pdecode2
+        cur_state = self.cur_state
+        dec_opcode_i = pdecode2.dec.raw_opcode_in # raw opcode
+
+        msr_read = Signal(reset=1)
+
+        with m.FSM(name='fetch_fsm'):
+
+            # waiting (zzz)
+            with m.State("IDLE"):
+                comb += fetch_pc_ready_o.eq(1)
+                with m.If(fetch_pc_valid_i):
+                    # instruction allowed to go: start by reading the PC
+                    # capture the PC and also drop it into Insn Memory
+                    # we have joined a pair of combinatorial memory
+                    # lookups together.  this is Generally Bad.
+                    comb += self.imem.a_pc_i.eq(pc)
+                    comb += self.imem.a_valid_i.eq(1)
+                    comb += self.imem.f_valid_i.eq(1)
+                    sync += cur_state.pc.eq(pc)
+                    sync += cur_state.svstate.eq(svstate) # and svstate
+
+                    # initiate read of MSR. arrives one clock later
+                    comb += self.state_r_msr.ren.eq(1 << StateRegs.MSR)
+                    sync += msr_read.eq(0)
+
+                    m.next = "INSN_READ"  # move to "wait for bus" phase
+
+            # dummy pause to find out why simulation is not keeping up
+            with m.State("INSN_READ"):
+                # one cycle later, msr/sv read arrives.  valid only once.
+                with m.If(~msr_read):
+                    sync += msr_read.eq(1) # yeah don't read it again
+                    sync += cur_state.msr.eq(self.state_r_msr.data_o)
+                with m.If(self.imem.f_busy_o): # zzz...
+                    # busy: stay in wait-read
+                    comb += self.imem.a_valid_i.eq(1)
+                    comb += self.imem.f_valid_i.eq(1)
+                with m.Else():
+                    # not busy: instruction fetched
+                    insn = get_insn(self.imem.f_instr_o, cur_state.pc)
+                    if self.svp64_en:
+                        svp64 = self.svp64
+                        # decode the SVP64 prefix, if any
+                        comb += svp64.raw_opcode_in.eq(insn)
+                        comb += svp64.bigendian.eq(self.core_bigendian_i)
+                        # pass the decoded prefix (if any) to PowerDecoder2
+                        sync += pdecode2.sv_rm.eq(svp64.svp64_rm)
+                        # remember whether this is a prefixed instruction, so
+                        # the FSM can readily loop when VL==0
+                        sync += is_svp64_mode.eq(svp64.is_svp64_mode)
+                        # calculate the address of the following instruction
+                        insn_size = Mux(svp64.is_svp64_mode, 8, 4)
+                        sync += nia.eq(cur_state.pc + insn_size)
+                        with m.If(~svp64.is_svp64_mode):
+                            # with no prefix, store the instruction
+                            # and hand it directly to the next FSM
+                            sync += dec_opcode_i.eq(insn)
+                            m.next = "INSN_READY"
+                        with m.Else():
+                            # fetch the rest of the instruction from memory
+                            comb += self.imem.a_pc_i.eq(cur_state.pc + 4)
+                            comb += self.imem.a_valid_i.eq(1)
+                            comb += self.imem.f_valid_i.eq(1)
+                            m.next = "INSN_READ2"
+                    else:
+                        # not SVP64 - 32-bit only
+                        sync += nia.eq(cur_state.pc + 4)
+                        sync += dec_opcode_i.eq(insn)
+                        m.next = "INSN_READY"
+
+            with m.State("INSN_READ2"):
+                with m.If(self.imem.f_busy_o):  # zzz...
+                    # busy: stay in wait-read
+                    comb += self.imem.a_valid_i.eq(1)
+                    comb += self.imem.f_valid_i.eq(1)
+                with m.Else():
+                    # not busy: instruction fetched
+                    insn = get_insn(self.imem.f_instr_o, cur_state.pc+4)
+                    sync += dec_opcode_i.eq(insn)
+                    m.next = "INSN_READY"
+                    # TODO: probably can start looking at pdecode2.rm_dec
+                    # here or maybe even in INSN_READ state, if svp64_mode
+                    # detected, in order to trigger - and wait for - the
+                    # predicate reading.
+                    if self.svp64_en:
+                        pmode = pdecode2.rm_dec.predmode
+                    """
+                    if pmode != SVP64PredMode.ALWAYS.value:
+                        fire predicate loading FSM and wait before
+                        moving to INSN_READY
+                    else:
+                        sync += self.srcmask.eq(-1) # set to all 1s
+                        sync += self.dstmask.eq(-1) # set to all 1s
+                        m.next = "INSN_READY"
+                    """
+
+            with m.State("INSN_READY"):
+                # hand over the instruction, to be decoded
+                comb += fetch_insn_valid_o.eq(1)
+                with m.If(fetch_insn_ready_i):
+                    m.next = "IDLE"
+
+    def fetch_predicate_fsm(self, m,
+                            pred_insn_valid_i, pred_insn_ready_o,
+                            pred_mask_valid_o, pred_mask_ready_i):
+        """fetch_predicate_fsm - obtains (constructs in the case of CR)
+           src/dest predicate masks
+
+        https://bugs.libre-soc.org/show_bug.cgi?id=617
+        the predicates can be read here, by using IntRegs r_ports['pred']
+        or CRRegs r_ports['pred'].  in the case of CRs it will have to
+        be done through multiple reads, extracting one relevant at a time.
+        later, a faster way would be to use the 32-bit-wide CR port but
+        this is more complex decoding, here.  equivalent code used in
+        ISACaller is "from soc.decoder.isa.caller import get_predcr"
+
+        note: this ENTIRE FSM is not to be called when svp64 is disabled
+        """
+        comb = m.d.comb
+        sync = m.d.sync
+        pdecode2 = self.pdecode2
+        rm_dec = pdecode2.rm_dec # SVP64RMModeDecode
+        predmode = rm_dec.predmode
+        srcpred, dstpred = rm_dec.srcpred, rm_dec.dstpred
+        cr_pred, int_pred = self.cr_pred, self.int_pred   # read regfiles
+
+        # elif predmode == CR:
+        #    CR-src sidx, sinvert = get_predcr(m, srcpred)
+        #    CR-dst didx, dinvert = get_predcr(m, dstpred)
+        #    TODO read CR-src and CR-dst into self.srcmask+dstmask with loop
+        #         has to cope with first one then the other
+        #    for cr_idx = FSM-state-loop(0..VL-1):
+        #        FSM-state-trigger-CR-read:
+        #               cr_ren = (1<<7-(cr_idx+SVP64CROffs.CRPred))
+        #               comb += cr_pred.ren.eq(cr_ren)
+        #        FSM-state-1-clock-later-actual-Read:
+        #               cr_field = Signal(4)
+        #               cr_bit = Signal(1)
+        #               # read the CR field, select the appropriate bit
+        #               comb += cr_field.eq(cr_pred.data_o)
+        #               comb += cr_bit.eq(cr_field.bit_select(idx)))
+        #               # just like in branch BO tests
+        #               comd += self.srcmask[cr_idx].eq(inv ^ cr_bit)
+
+        # decode predicates
+        sregread, sinvert, sunary, sall1s = get_predint(m, srcpred, 's')
+        dregread, dinvert, dunary, dall1s = get_predint(m, dstpred, 'd')
+        sidx, scrinvert = get_predcr(m, srcpred, 's')
+        didx, dcrinvert = get_predcr(m, dstpred, 'd')
+
+        with m.FSM(name="fetch_predicate"):
+
+            with m.State("FETCH_PRED_IDLE"):
+                comb += pred_insn_ready_o.eq(1)
+                with m.If(pred_insn_valid_i):
+                    with m.If(predmode == SVP64PredMode.INT):
+                        # skip fetching destination mask register, when zero
+                        with m.If(dall1s):
+                            sync += self.dstmask.eq(-1)
+                            # directly go to fetch source mask register
+                            # guaranteed not to be zero (otherwise predmode
+                            # would be SVP64PredMode.ALWAYS, not INT)
+                            comb += int_pred.addr.eq(sregread)
+                            comb += int_pred.ren.eq(1)
+                            m.next = "INT_SRC_READ"
+                        # fetch destination predicate register
+                        with m.Else():
+                            comb += int_pred.addr.eq(dregread)
+                            comb += int_pred.ren.eq(1)
+                            m.next = "INT_DST_READ"
+                    with m.Else():
+                        sync += self.srcmask.eq(-1)
+                        sync += self.dstmask.eq(-1)
+                        m.next = "FETCH_PRED_DONE"
+
+            with m.State("INT_DST_READ"):
+                # store destination mask
+                inv = Repl(dinvert, 64)
+                sync += self.dstmask.eq(self.int_pred.data_o ^ inv)
+                # skip fetching source mask register, when zero
+                with m.If(sall1s):
+                    sync += self.srcmask.eq(-1)
+                    m.next = "FETCH_PRED_DONE"
+                # fetch source predicate register
+                with m.Else():
+                    comb += int_pred.addr.eq(sregread)
+                    comb += int_pred.ren.eq(1)
+                    m.next = "INT_SRC_READ"
+
+            with m.State("INT_SRC_READ"):
+                # store source mask
+                inv = Repl(sinvert, 64)
+                sync += self.srcmask.eq(self.int_pred.data_o ^ inv)
+                m.next = "FETCH_PRED_DONE"
+
+            with m.State("FETCH_PRED_DONE"):
+                comb += pred_mask_valid_o.eq(1)
+                with m.If(pred_mask_ready_i):
+                    m.next = "FETCH_PRED_IDLE"
+
+    def issue_fsm(self, m, core, pc_changed, sv_changed, nia,
+                  dbg, core_rst, is_svp64_mode,
+                  fetch_pc_ready_o, fetch_pc_valid_i,
+                  fetch_insn_valid_o, fetch_insn_ready_i,
+                  pred_insn_valid_i, pred_insn_ready_o,
+                  pred_mask_valid_o, pred_mask_ready_i,
+                  exec_insn_valid_i, exec_insn_ready_o,
+                  exec_pc_valid_o, exec_pc_ready_i):
+        """issue FSM
+
+        decode / issue FSM.  this interacts with the "fetch" FSM
+        through fetch_insn_ready/valid (incoming) and fetch_pc_ready/valid
+        (outgoing). also interacts with the "execute" FSM
+        through exec_insn_ready/valid (outgoing) and exec_pc_ready/valid
+        (incoming).
+        SVP64 RM prefixes have already been set up by the
+        "fetch" phase, so execute is fairly straightforward.
+        """
+
+        comb = m.d.comb
+        sync = m.d.sync
+        pdecode2 = self.pdecode2
+        cur_state = self.cur_state
+
+        # temporaries
+        dec_opcode_i = pdecode2.dec.raw_opcode_in # raw opcode
+
+        # for updating svstate (things like srcstep etc.)
+        update_svstate = Signal() # set this (below) if updating
+        new_svstate = SVSTATERec("new_svstate")
+        comb += new_svstate.eq(cur_state.svstate)
+
+        # precalculate srcstep+1 and dststep+1
+        cur_srcstep = cur_state.svstate.srcstep
+        cur_dststep = cur_state.svstate.dststep
+        next_srcstep = Signal.like(cur_srcstep)
+        next_dststep = Signal.like(cur_dststep)
+        comb += next_srcstep.eq(cur_state.svstate.srcstep+1)
+        comb += next_dststep.eq(cur_state.svstate.dststep+1)
+
+        with m.FSM(name="issue_fsm"):
+
+            # sync with the "fetch" phase which is reading the instruction
+            # at this point, there is no instruction running, that
+            # could inadvertently update the PC.
+            with m.State("ISSUE_START"):
+                # wait on "core stop" release, before next fetch
+                # need to do this here, in case we are in a VL==0 loop
+                with m.If(~dbg.core_stop_o & ~core_rst):
+                    comb += fetch_pc_valid_i.eq(1) # tell fetch to start
+                    with m.If(fetch_pc_ready_o):   # fetch acknowledged us
+                        m.next = "INSN_WAIT"
+                with m.Else():
+                    # tell core it's stopped, and acknowledge debug handshake
+                    comb += core.core_stopped_i.eq(1)
+                    comb += dbg.core_stopped_i.eq(1)
+                    # while stopped, allow updating the PC and SVSTATE
+                    with m.If(self.pc_i.ok):
+                        comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
+                        comb += self.state_w_pc.data_i.eq(self.pc_i.data)
+                        sync += pc_changed.eq(1)
+                    with m.If(self.svstate_i.ok):
+                        comb += new_svstate.eq(self.svstate_i.data)
+                        comb += update_svstate.eq(1)
+                        sync += sv_changed.eq(1)
+
+            # wait for an instruction to arrive from Fetch
+            with m.State("INSN_WAIT"):
+                comb += fetch_insn_ready_i.eq(1)
+                with m.If(fetch_insn_valid_o):
+                    # loop into ISSUE_START if it's a SVP64 instruction
+                    # and VL == 0.  this because VL==0 is a for-loop
+                    # from 0 to 0 i.e. always, always a NOP.
+                    cur_vl = cur_state.svstate.vl
+                    with m.If(is_svp64_mode & (cur_vl == 0)):
+                        # update the PC before fetching the next instruction
+                        # since we are in a VL==0 loop, no instruction was
+                        # executed that we could be overwriting
+                        comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
+                        comb += self.state_w_pc.data_i.eq(nia)
+                        comb += self.insn_done.eq(1)
+                        m.next = "ISSUE_START"
+                    with m.Else():
+                        if self.svp64_en:
+                            m.next = "PRED_START"  # start fetching predicate
+                        else:
+                            m.next = "DECODE_SV"  # skip predication
+
+            with m.State("PRED_START"):
+                comb += pred_insn_valid_i.eq(1)  # tell fetch_pred to start
+                with m.If(pred_insn_ready_o):  # fetch_pred acknowledged us
+                    m.next = "MASK_WAIT"
+
+            with m.State("MASK_WAIT"):
+                comb += pred_mask_ready_i.eq(1) # ready to receive the masks
+                with m.If(pred_mask_valid_o): # predication masks are ready
+                    # with m.If(is_svp64_mode):
+                    #    TODO advance src/dst step to "skip" over predicated-out
+                    #    from self.srcmask and self.dstmask
+                    #    https://bugs.libre-soc.org/show_bug.cgi?id=617#c3
+                    #    but still without exceeding VL in either case
+                    # IMPORTANT: when changing src/dest step, have to
+                    # jump to m.next = "DECODE_SV" to deal with the change in
+                    # SVSTATE
+
+                    with m.If(is_svp64_mode):
+                        if self.svp64_en:
+                            pred_src_zero = pdecode2.rm_dec.pred_sz
+                            pred_dst_zero = pdecode2.rm_dec.pred_dz
+
+                        """
+                        TODO: actually, can use
+                        PriorityEncoder(self.srcmask | (1<<cur_srcstep))
+
+                        if not pred_src_zero:
+                            if (((1<<cur_srcstep) & self.srcmask) == 0) and
+                                  (cur_srcstep != vl):
+                                comb += update_svstate.eq(1)
+                                comb += new_svstate.srcstep.eq(next_srcstep)
+
+                        if not pred_dst_zero:
+                            if (((1<<cur_dststep) & self.dstmask) == 0) and
+                                  (cur_dststep != vl):
+                                comb += new_svstate.dststep.eq(next_dststep)
+                                comb += update_svstate.eq(1)
+
+                        if update_svstate:
+                            m.next = "DECODE_SV"
+                        """
+
+                    m.next = "DECODE_SV"
+
+            # after src/dst step have been updated, we are ready
+            # to decode the instruction
+            with m.State("DECODE_SV"):
+                # decode the instruction
+                sync += core.e.eq(pdecode2.e)
+                sync += core.state.eq(cur_state)
+                sync += core.raw_insn_i.eq(dec_opcode_i)
+                sync += core.bigendian_i.eq(self.core_bigendian_i)
+                # set RA_OR_ZERO detection in satellite decoders
+                sync += core.sv_a_nz.eq(pdecode2.sv_a_nz)
+                m.next = "INSN_EXECUTE"  # move to "execute"
+
+            # handshake with execution FSM, move to "wait" once acknowledged
+            with m.State("INSN_EXECUTE"):
+                comb += exec_insn_valid_i.eq(1) # trigger execute
+                with m.If(exec_insn_ready_o):   # execute acknowledged us
+                    m.next = "EXECUTE_WAIT"
+
+            with m.State("EXECUTE_WAIT"):
+                # wait on "core stop" release, at instruction end
+                # need to do this here, in case we are in a VL>1 loop
+                with m.If(~dbg.core_stop_o & ~core_rst):
+                    comb += exec_pc_ready_i.eq(1)
+                    with m.If(exec_pc_valid_o):
+
+                        # was this the last loop iteration?
+                        is_last = Signal()
+                        cur_vl = cur_state.svstate.vl
+                        comb += is_last.eq(next_srcstep == cur_vl)
+
+                        # if either PC or SVSTATE were changed by the previous
+                        # instruction, go directly back to Fetch, without
+                        # updating either PC or SVSTATE
+                        with m.If(pc_changed | sv_changed):
+                            m.next = "ISSUE_START"
+
+                        # also return to Fetch, when no output was a vector
+                        # (regardless of SRCSTEP and VL), or when the last
+                        # instruction was really the last one of the VL loop
+                        with m.Elif((~pdecode2.loop_continue) | is_last):
+                            # before going back to fetch, update the PC state
+                            # register with the NIA.
+                            # ok here we are not reading the branch unit.
+                            # TODO: this just blithely overwrites whatever
+                            #       pipeline updated the PC
+                            comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
+                            comb += self.state_w_pc.data_i.eq(nia)
+                            # reset SRCSTEP before returning to Fetch
+                            with m.If(pdecode2.loop_continue):
+                                comb += new_svstate.srcstep.eq(0)
+                                comb += new_svstate.dststep.eq(0)
+                                comb += update_svstate.eq(1)
+                            m.next = "ISSUE_START"
+
+                        # returning to Execute? then, first update SRCSTEP
+                        with m.Else():
+                            comb += new_svstate.srcstep.eq(next_srcstep)
+                            comb += new_svstate.dststep.eq(next_dststep)
+                            comb += update_svstate.eq(1)
+                            m.next = "DECODE_SV"
+
+                with m.Else():
+                    comb += core.core_stopped_i.eq(1)
+                    comb += dbg.core_stopped_i.eq(1)
+                    # while stopped, allow updating the PC and SVSTATE
+                    with m.If(self.pc_i.ok):
+                        comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
+                        comb += self.state_w_pc.data_i.eq(self.pc_i.data)
+                        sync += pc_changed.eq(1)
+                    with m.If(self.svstate_i.ok):
+                        comb += new_svstate.eq(self.svstate_i.data)
+                        comb += update_svstate.eq(1)
+                        sync += sv_changed.eq(1)
+
+        # check if svstate needs updating: if so, write it to State Regfile
+        with m.If(update_svstate):
+            comb += self.state_w_sv.wen.eq(1<<StateRegs.SVSTATE)
+            comb += self.state_w_sv.data_i.eq(new_svstate)
+            sync += cur_state.svstate.eq(new_svstate) # for next clock
+
+    def execute_fsm(self, m, core, pc_changed, sv_changed,
+                    exec_insn_valid_i, exec_insn_ready_o,
+                    exec_pc_valid_o, exec_pc_ready_i):
+        """execute FSM
+
+        execute FSM. this interacts with the "issue" FSM
+        through exec_insn_ready/valid (incoming) and exec_pc_ready/valid
+        (outgoing). SVP64 RM prefixes have already been set up by the
+        "issue" phase, so execute is fairly straightforward.
+        """
+
+        comb = m.d.comb
+        sync = m.d.sync
+        pdecode2 = self.pdecode2
+
+        # temporaries
+        core_busy_o = core.busy_o                 # core is busy
+        core_ivalid_i = core.ivalid_i             # instruction is valid
+        core_issue_i = core.issue_i               # instruction is issued
+        insn_type = core.e.do.insn_type           # instruction MicroOp type
+
+        with m.FSM(name="exec_fsm"):
+
+            # waiting for instruction bus (stays there until not busy)
+            with m.State("INSN_START"):
+                comb += exec_insn_ready_o.eq(1)
+                with m.If(exec_insn_valid_i):
+                    comb += core_ivalid_i.eq(1)  # instruction is valid
+                    comb += core_issue_i.eq(1)  # and issued
+                    sync += sv_changed.eq(0)
+                    sync += pc_changed.eq(0)
+                    m.next = "INSN_ACTIVE"  # move to "wait completion"
+
+            # instruction started: must wait till it finishes
+            with m.State("INSN_ACTIVE"):
+                with m.If(insn_type != MicrOp.OP_NOP):
+                    comb += core_ivalid_i.eq(1) # instruction is valid
+                # note changes to PC and SVSTATE
+                with m.If(self.state_nia.wen & (1<<StateRegs.SVSTATE)):
+                    sync += sv_changed.eq(1)
+                with m.If(self.state_nia.wen & (1<<StateRegs.PC)):
+                    sync += pc_changed.eq(1)
+                with m.If(~core_busy_o): # instruction done!
+                    comb += exec_pc_valid_o.eq(1)
+                    with m.If(exec_pc_ready_i):
+                        comb += self.insn_done.eq(1)
+                        m.next = "INSN_START"  # back to fetch
+
+    def setup_peripherals(self, m):
         comb, sync = m.d.comb, m.d.sync
 
         m.submodules.core = core = DomainRenamer("coresync")(self.core)
@@ -148,6 +749,12 @@ class TestIssuerInternal(Elaboratable):
 
         cur_state = self.cur_state
 
+        # 4x 4k SRAM blocks.  these simply "exist", they get routed in litex
+        if self.sram4x4k:
+            for i, sram in enumerate(self.sram4k):
+                m.submodules["sram4k_%d" % i] = sram
+                comb += sram.enable.eq(self.wb_sram_en)
+
         # XICS interrupt handler
         if self.xics:
             m.submodules.xics_icp = icp = self.xics_icp
@@ -168,7 +775,8 @@ class TestIssuerInternal(Elaboratable):
         # instruction decoder
         pdecode = create_pdecode()
         m.submodules.dec2 = pdecode2 = self.pdecode2
-        m.submodules.svp64 = svp64 = self.svp64
+        if self.svp64_en:
+            m.submodules.svp64 = svp64 = self.svp64
 
         # convenience
         dmi, d_reg, d_cr, d_xer, = dbg.dmi, dbg.d_gpr, dbg.d_cr, dbg.d_xer
@@ -202,217 +810,133 @@ class TestIssuerInternal(Elaboratable):
         m.d.comb += ldst.ad.go_i.eq(ldst.ad.rel_o) # link addr-go direct to rel
         m.d.comb += ldst.st.go_i.eq(st_go_edge) # link store-go to rising rel
 
+        return core_rst
+
+    def elaborate(self, platform):
+        m = Module()
+        # convenience
+        comb, sync = m.d.comb, m.d.sync
+        cur_state = self.cur_state
+        pdecode2 = self.pdecode2
+        dbg = self.dbg
+        core = self.core
+
+        # set up peripherals and core
+        core_rst = self.setup_peripherals(m)
+
         # PC and instruction from I-Memory
-        pc_changed = Signal() # note write to PC
         comb += self.pc_o.eq(cur_state.pc)
-        ilatch = Signal(32)
-
-        # address of the next instruction, in the absence of a branch
-        # depends on the instruction size
-        nia = Signal(64, reset_less=True)
+        pc_changed = Signal() # note write to PC
+        sv_changed = Signal() # note write to SVSTATE
 
-        # read the PC
-        pc = Signal(64, reset_less=True)
-        pc_ok_delay = Signal()
-        sync += pc_ok_delay.eq(~self.pc_i.ok)
-        with m.If(self.pc_i.ok):
-            # incoming override (start from pc_i)
-            comb += pc.eq(self.pc_i.data)
-        with m.Else():
-            # otherwise read StateRegs regfile for PC...
-            comb += self.state_r_pc.ren.eq(1<<StateRegs.PC)
-        # ... but on a 1-clock delay
-        with m.If(pc_ok_delay):
-            comb += pc.eq(self.state_r_pc.data_o)
+        # read state either from incoming override or from regfile
+        # TODO: really should be doing MSR in the same way
+        pc = state_get(m, self.pc_i, "pc",                  # read PC
+                            self.state_r_pc, StateRegs.PC)
+        svstate = state_get(m, self.svstate_i, "svstate",   # read SVSTATE
+                            self.state_r_sv, StateRegs.SVSTATE)
 
         # don't write pc every cycle
         comb += self.state_w_pc.wen.eq(0)
         comb += self.state_w_pc.data_i.eq(0)
 
-        # don't read msr or svstate every cycle
-        comb += self.state_r_sv.ren.eq(0)
+        # don't read msr every cycle
         comb += self.state_r_msr.ren.eq(0)
-        msr_read = Signal(reset=1)
-        sv_read = Signal(reset=1)
+
+        # address of the next instruction, in the absence of a branch
+        # depends on the instruction size
+        nia = Signal(64, reset_less=True)
 
         # connect up debug signals
         # TODO comb += core.icache_rst_i.eq(dbg.icache_rst_o)
         comb += dbg.terminate_i.eq(core.core_terminate_o)
         comb += dbg.state.pc.eq(pc)
-        #comb += dbg.state.pc.eq(cur_state.pc)
+        comb += dbg.state.svstate.eq(svstate)
         comb += dbg.state.msr.eq(cur_state.msr)
 
-        # temporaries
-        core_busy_o = core.busy_o                 # core is busy
-        core_ivalid_i = core.ivalid_i             # instruction is valid
-        core_issue_i = core.issue_i               # instruction is issued
-        dec_opcode_i = pdecode2.dec.raw_opcode_in # raw opcode
-        insn_type = core.e.do.insn_type           # instruction MicroOp type
+        # pass the prefix mode from Fetch to Issue, so the latter can loop
+        # on VL==0
+        is_svp64_mode = Signal()
 
-        # there are *TWO* FSMs, one fetch (32/64-bit) one decode/execute.
+        # there are *THREE* FSMs, fetch (32/64-bit) issue, decode/execute.
         # these are the handshake signals between fetch and decode/execute
 
         # fetch FSM can run as soon as the PC is valid
-        fetch_pc_valid_i = Signal()
-        fetch_pc_ready_o = Signal()
-        # when done, deliver the instruction to the next FSM
+        fetch_pc_valid_i = Signal() # Execute tells Fetch "start next read"
+        fetch_pc_ready_o = Signal() # Fetch Tells SVSTATE "proceed"
+
+        # fetch FSM hands over the instruction to be decoded / issued
         fetch_insn_valid_o = Signal()
         fetch_insn_ready_i = Signal()
 
-        # latches copy of raw fetched instruction
-        fetch_insn_o = Signal(32, reset_less=True)
+        # predicate fetch FSM decodes and fetches the predicate
+        pred_insn_valid_i = Signal()
+        pred_insn_ready_o = Signal()
 
-        # actually use a nmigen FSM for the first time (w00t)
-        # this FSM is perhaps unusual in that it detects conditions
-        # then "holds" information, combinatorially, for the core
-        # (as opposed to using sync - which would be on a clock's delay)
-        # this includes the actual opcode, valid flags and so on.
+        # predicate fetch FSM delivers the masks
+        pred_mask_valid_o = Signal()
+        pred_mask_ready_i = Signal()
 
-        # this FSM performs fetch of raw instruction data, partial-decodes
-        # it 32-bit at a time to detect SVP64 prefixes, and will optionally
-        # read a 2nd 32-bit quantity if that occurs.
+        # issue FSM delivers the instruction to the be executed
+        exec_insn_valid_i = Signal()
+        exec_insn_ready_o = Signal()
 
-        with m.FSM(name='fetch_fsm'):
+        # execute FSM, hands over the PC/SVSTATE back to the issue FSM
+        exec_pc_valid_o = Signal()
+        exec_pc_ready_i = Signal()
 
-            # waiting (zzz)
-            with m.State("IDLE"):
-                with m.If(~dbg.core_stop_o & ~core_rst):
-                    comb += fetch_pc_ready_o.eq(1)
-                    with m.If(fetch_pc_valid_i):
-                        # instruction allowed to go: start by reading the PC
-                        # capture the PC and also drop it into Insn Memory
-                        # we have joined a pair of combinatorial memory
-                        # lookups together.  this is Generally Bad.
-                        comb += self.imem.a_pc_i.eq(pc)
-                        comb += self.imem.a_valid_i.eq(1)
-                        comb += self.imem.f_valid_i.eq(1)
-                        sync += cur_state.pc.eq(pc)
-
-                        # initiate read of MSR/SVSTATE. arrives one clock later
-                        comb += self.state_r_msr.ren.eq(1 << StateRegs.MSR)
-                        comb += self.state_r_sv.ren.eq(1 << StateRegs.SVSTATE)
-                        sync += msr_read.eq(0)
-                        sync += sv_read.eq(0)
-
-                        m.next = "INSN_READ"  # move to "wait for bus" phase
-                with m.Else():
-                    comb += core.core_stopped_i.eq(1)
-                    comb += dbg.core_stopped_i.eq(1)
+        # the FSMs here are perhaps unusual in that they detect conditions
+        # then "hold" information, combinatorially, for the core
+        # (as opposed to using sync - which would be on a clock's delay)
+        # this includes the actual opcode, valid flags and so on.
 
-            # dummy pause to find out why simulation is not keeping up
-            with m.State("INSN_READ"):
-                # one cycle later, msr/sv read arrives.  valid only once.
-                with m.If(~msr_read):
-                    sync += msr_read.eq(1) # yeah don't read it again
-                    sync += cur_state.msr.eq(self.state_r_msr.data_o)
-                with m.If(~sv_read):
-                    sync += sv_read.eq(1) # yeah don't read it again
-                    sync += cur_state.svstate.eq(self.state_r_sv.data_o)
-                with m.If(self.imem.f_busy_o): # zzz...
-                    # busy: stay in wait-read
-                    comb += self.imem.a_valid_i.eq(1)
-                    comb += self.imem.f_valid_i.eq(1)
-                with m.Else():
-                    # not busy: instruction fetched
-                    insn = get_insn(self.imem.f_instr_o, cur_state.pc)
-                    # decode the SVP64 prefix, if any
-                    comb += svp64.raw_opcode_in.eq(insn)
-                    comb += svp64.bigendian.eq(self.core_bigendian_i)
-                    # pass the decoded prefix (if any) to PowerDecoder2
-                    sync += pdecode2.sv_rm.eq(svp64.svp64_rm)
-                    # calculate the address of the following instruction
-                    insn_size = Mux(svp64.is_svp64_mode, 8, 4)
-                    sync += nia.eq(cur_state.pc + insn_size)
-                    with m.If(~svp64.is_svp64_mode):
-                        # with no prefix, store the instruction
-                        # and hand it directly to the next FSM
-                        sync += fetch_insn_o.eq(insn)
-                        m.next = "INSN_READY"
-                    with m.Else():
-                        # fetch the rest of the instruction from memory
-                        comb += self.imem.a_pc_i.eq(cur_state.pc + 4)
-                        comb += self.imem.a_valid_i.eq(1)
-                        comb += self.imem.f_valid_i.eq(1)
-                        m.next = "INSN_READ2"
+        # Fetch, then predicate fetch, then Issue, then Execute.
+        # Issue is where the VL for-loop # lives.  the ready/valid
+        # signalling is used to communicate between the four.
 
-            with m.State("INSN_READ2"):
-                with m.If(self.imem.f_busy_o):  # zzz...
-                    # busy: stay in wait-read
-                    comb += self.imem.a_valid_i.eq(1)
-                    comb += self.imem.f_valid_i.eq(1)
-                with m.Else():
-                    # not busy: instruction fetched
-                    insn = get_insn(self.imem.f_instr_o, cur_state.pc+4)
-                    sync += fetch_insn_o.eq(insn)
-                    m.next = "INSN_READY"
+        self.fetch_fsm(m, core, pc, svstate, nia, is_svp64_mode,
+                       fetch_pc_ready_o, fetch_pc_valid_i,
+                       fetch_insn_valid_o, fetch_insn_ready_i)
 
-            with m.State("INSN_READY"):
-                # hand over the instruction, to be decoded
-                comb += fetch_insn_valid_o.eq(1)
-                with m.If(fetch_insn_ready_i):
-                    m.next = "IDLE"
+        self.issue_fsm(m, core, pc_changed, sv_changed, nia,
+                       dbg, core_rst, is_svp64_mode,
+                       fetch_pc_ready_o, fetch_pc_valid_i,
+                       fetch_insn_valid_o, fetch_insn_ready_i,
+                       pred_insn_valid_i, pred_insn_ready_o,
+                       pred_mask_valid_o, pred_mask_ready_i,
+                       exec_insn_valid_i, exec_insn_ready_o,
+                       exec_pc_valid_o, exec_pc_ready_i)
 
-        # decode / issue / execute FSM.  this interacts with the "fetch" FSM
-        # through fetch_pc_ready/valid (incoming) and fetch_insn_ready/valid
-        # (outgoing).  SVP64 RM prefixes have already been set up by the
-        # "fetch" phase, so execute is fairly straightforward.
+        if self.svp64_en:
+            self.fetch_predicate_fsm(m,
+                                     pred_insn_valid_i, pred_insn_ready_o,
+                                     pred_mask_valid_o, pred_mask_ready_i)
 
-        with m.FSM():
+        self.execute_fsm(m, core, pc_changed, sv_changed,
+                         exec_insn_valid_i, exec_insn_ready_o,
+                         exec_pc_valid_o, exec_pc_ready_i)
 
-            # go fetch the instruction at the current PC
-            # at this point, there is no instruction running, that
-            # could inadvertently update the PC.
-            with m.State("INSN_FETCH"):
-                comb += fetch_pc_valid_i.eq(1)
-                with m.If(fetch_pc_ready_o):
-                    m.next = "INSN_WAIT"
+        # this bit doesn't have to be in the FSM: connect up to read
+        # regfiles on demand from DMI
+        self.do_dmi(m, dbg)
 
-            # decode the instruction when it arrives
-            with m.State("INSN_WAIT"):
-                comb += fetch_insn_ready_i.eq(1)
-                with m.If(fetch_insn_valid_o):
-                    # decode the instruction
-                    # TODO, before issuing new instruction first
-                    # check if it's SVP64. (svp64.is_svp64_mode set)
-                    # if yes, record the svp64_rm, put that into
-                    # pdecode2.sv_rm, then read another 32 bits (INSN_FETCH2?)
-                    comb += dec_opcode_i.eq(fetch_insn_o)  # actual opcode
-                    sync += core.e.eq(pdecode2.e)
-                    sync += core.state.eq(cur_state)
-                    sync += core.raw_insn_i.eq(dec_opcode_i)
-                    sync += core.bigendian_i.eq(self.core_bigendian_i)
-                    sync += ilatch.eq(insn) # latch current insn
-                    # also drop PC and MSR into decode "state"
-                    m.next = "INSN_START" # move to "start"
+        # DEC and TB inc/dec FSM.  copy of DEC is put into CoreState,
+        # (which uses that in PowerDecoder2 to raise 0x900 exception)
+        self.tb_dec_fsm(m, cur_state.dec)
 
-            # waiting for instruction bus (stays there until not busy)
-            with m.State("INSN_START"):
-                comb += core_ivalid_i.eq(1) # instruction is valid
-                comb += core_issue_i.eq(1)  # and issued
-                sync += pc_changed.eq(0)
+        return m
 
-                m.next = "INSN_ACTIVE" # move to "wait completion"
+    def do_dmi(self, m, dbg):
+        """deals with DMI debug requests
 
-            # instruction started: must wait till it finishes
-            with m.State("INSN_ACTIVE"):
-                with m.If(insn_type != MicrOp.OP_NOP):
-                    comb += core_ivalid_i.eq(1) # instruction is valid
-                with m.If(self.state_nia.wen & (1<<StateRegs.PC)):
-                    sync += pc_changed.eq(1)
-                with m.If(~core_busy_o): # instruction done!
-                    # ok here we are not reading the branch unit.  TODO
-                    # this just blithely overwrites whatever pipeline
-                    # updated the PC
-                    with m.If(~pc_changed):
-                        comb += self.state_w_pc.wen.eq(1<<StateRegs.PC)
-                        comb += self.state_w_pc.data_i.eq(nia)
-                    sync += core.e.eq(0)
-                    sync += core.raw_insn_i.eq(0)
-                    sync += core.bigendian_i.eq(0)
-                    m.next = "INSN_FETCH"  # back to fetch
+        currently only provides read requests for the INT regfile, CR and XER
+        it will later also deal with *writing* to these regfiles.
+        """
+        comb = m.d.comb
+        sync = m.d.sync
+        dmi, d_reg, d_cr, d_xer, = dbg.dmi, dbg.d_gpr, dbg.d_cr, dbg.d_xer
+        intrf = self.core.regs.rf['int']
 
-        # this bit doesn't have to be in the FSM: connect up to read
-        # regfiles on demand from DMI
         with m.If(d_reg.req): # request for regfile access being made
             # TODO: error-check this
             # XXX should this be combinatorial?  sync better?
@@ -448,12 +972,6 @@ class TestIssuerInternal(Elaboratable):
             comb += d_xer.data.eq(self.xer_r.data_o)
             comb += d_xer.ack.eq(1)
 
-        # DEC and TB inc/dec FSM.  copy of DEC is put into CoreState,
-        # (which uses that in PowerDecoder2 to raise 0x900 exception)
-        self.tb_dec_fsm(m, cur_state.dec)
-
-        return m
-
     def tb_dec_fsm(self, m, spr_dec):
         """tb_dec_fsm
 
@@ -532,6 +1050,10 @@ class TestIssuerInternal(Elaboratable):
         ports += list(self.imem.ibus.fields.values())
         ports += list(self.core.l0.cmpi.lsmem.lsi.slavebus.fields.values())
 
+        if self.sram4x4k:
+            for sram in self.sram4k:
+                ports += list(sram.bus.fields.values())
+
         if self.xics:
             ports += list(self.xics_icp.bus.fields.values())
             ports += list(self.xics_ics.bus.fields.values())