X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fsoc%2Fsimulator%2Ftest_mul_sim.py;h=6d251056aeb34041927ec1f7773935627e894382;hb=5963eef6679f6833b6b8f854868d90480e3753b2;hp=a3db0f133d648095aec6cdd4700e623f89b521ac;hpb=29f89540ab8f8d94a78f5b96801b76f3a06a0311;p=soc.git

diff --git a/src/soc/simulator/test_mul_sim.py b/src/soc/simulator/test_mul_sim.py
index a3db0f13..6d251056 100644
--- a/src/soc/simulator/test_mul_sim.py
+++ b/src/soc/simulator/test_mul_sim.py
@@ -1,9 +1,9 @@
 from nmigen import Module, Signal
 from nmigen.back.pysim import Simulator, Delay, Settle
-from nmigen.test.utils import FHDLTestCase
+from nmutil.formaltest import FHDLTestCase
 import unittest
 from soc.decoder.power_decoder import (create_pdecode)
-from soc.decoder.power_enums import (Function, InternalOp,
+from soc.decoder.power_enums import (Function, MicrOp,
                                      In1Sel, In2Sel, In3Sel,
                                      OutSel, RC, LdstLen, CryIn,
                                      single_bit_flags, Form, SPR,
@@ -14,6 +14,7 @@ from soc.simulator.qemu import run_program
 from soc.decoder.isa.all import ISA
 from soc.fu.test.common import TestCase
 from soc.simulator.test_sim import DecoderBase
+from soc.config.endian import bigendian
 
 
 
@@ -28,7 +29,7 @@ class MulTestCases(FHDLTestCase):
         lst = ["addi 1, 0, 0x5678",
                "addi 2, 0, 0x1234",
                "mullw 3, 1, 2"]
-        self.run_tst_program(Program(lst), [3])
+        self.run_tst_program(Program(lst, bigendian), [3])
 
     def test_mullwo(self):
         lst = ["addi 1, 0, 0x5678",
@@ -36,7 +37,7 @@ class MulTestCases(FHDLTestCase):
                "addi 2, 0, 0x1234",
                "neg 2, 2",
                "mullwo 3, 1, 2"]
-        self.run_tst_program(Program(lst), [3])
+        self.run_tst_program(Program(lst, bigendian), [3])
 
     def run_tst_program(self, prog, initial_regs=None, initial_sprs=None,
                                     initial_mem=None):