X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fsoc%2Fsimulator%2Ftest_mul_sim.py;h=6d251056aeb34041927ec1f7773935627e894382;hb=5963eef6679f6833b6b8f854868d90480e3753b2;hp=ef117c3a2d127f25087091ac63786002fdc41b42;hpb=b92b8d7f87b8700d879413579d996690d0fda17f;p=soc.git

diff --git a/src/soc/simulator/test_mul_sim.py b/src/soc/simulator/test_mul_sim.py
index ef117c3a..6d251056 100644
--- a/src/soc/simulator/test_mul_sim.py
+++ b/src/soc/simulator/test_mul_sim.py
@@ -1,6 +1,6 @@
 from nmigen import Module, Signal
 from nmigen.back.pysim import Simulator, Delay, Settle
-from nmigen.test.utils import FHDLTestCase
+from nmutil.formaltest import FHDLTestCase
 import unittest
 from soc.decoder.power_decoder import (create_pdecode)
 from soc.decoder.power_enums import (Function, MicrOp,