X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fsoc%2Fsimulator%2Ftest_sim.py;h=d1e65f4fcdb017f2679dde9f4d6ba3da18035fa7;hb=9ecfd06b8498e5ac86eecf7b990053e3cb9ed903;hp=de4193bc5f3bacd7311a984682e728c52484b6a4;hpb=32db050bdcccd20dbe1437d6f81d74f3ff2c9ceb;p=soc.git diff --git a/src/soc/simulator/test_sim.py b/src/soc/simulator/test_sim.py index de4193bc..d1e65f4f 100644 --- a/src/soc/simulator/test_sim.py +++ b/src/soc/simulator/test_sim.py @@ -13,11 +13,33 @@ from soc.simulator.program import Program from soc.simulator.qemu import run_program from soc.decoder.isa.all import ISA from soc.fu.test.common import TestCase +from soc.config.endian import bigendian -class Register: - def __init__(self, num): - self.num = num +class AttnTestCase(FHDLTestCase): + test_data = [] + + def __init__(self, name="general"): + super().__init__(name) + self.test_name = name + + def test_0_attn(self): + """simple test of attn. program is 4 long: should halt at 2nd op + """ + lst = ["addi 6, 0, 0x10", + "attn", + "subf. 1, 6, 7", + "cmp cr2, 1, 6, 7", + ] + with Program(lst, bigendian) as program: + self.run_tst_program(program, [1]) + + def run_tst_program(self, prog, initial_regs=None, initial_sprs=None, + initial_mem=None): + initial_regs = [0] * 32 + tc = TestCase(prog, self.test_name, initial_regs, initial_sprs, 0, + initial_mem, 0) + self.test_data.append(tc) class GeneralTestCases(FHDLTestCase): @@ -34,7 +56,7 @@ class GeneralTestCases(FHDLTestCase): "subf. 1, 6, 7", "cmp cr2, 1, 6, 7", ] - with Program(lst) as program: + with Program(lst, bigendian) as program: self.run_tst_program(program, [1]) @unittest.skip("disable") @@ -43,7 +65,7 @@ class GeneralTestCases(FHDLTestCase): "addi 2, 0, 0x1234", "add 3, 1, 2", "and 4, 1, 2"] - with Program(lst) as program: + with Program(lst, bigendian) as program: self.run_tst_program(program, [1, 2, 3, 4]) @unittest.skip("disable") @@ -56,7 +78,7 @@ class GeneralTestCases(FHDLTestCase): initial_mem = {0x1230: (0x5432123412345678, 8), 0x1238: (0xabcdef0187654321, 8), } - with Program(lst) as program: + with Program(lst, bigendian) as program: self.run_tst_program(program, [1, 2, 3], initial_mem) @@ -68,7 +90,7 @@ class GeneralTestCases(FHDLTestCase): "addi 4, 0, 0x40", "stw 1, 0x40(2)", "lwbrx 3, 4, 2"] - with Program(lst) as program: + with Program(lst, bigendian) as program: self.run_tst_program(program, [1, 2, 3]) @unittest.skip("disable") @@ -78,7 +100,7 @@ class GeneralTestCases(FHDLTestCase): "addi 4, 0, 0x40", "stwbrx 1, 4, 2", "lwzx 3, 4, 2"] - with Program(lst) as program: + with Program(lst, bigendian) as program: self.run_tst_program(program, [1, 2, 3]) @unittest.skip("disable") @@ -88,7 +110,7 @@ class GeneralTestCases(FHDLTestCase): "addi 4, 0, 0x40", "stw 1, 0x40(2)", "lwzx 3, 4, 2"] - with Program(lst) as program: + with Program(lst, bigendian) as program: self.run_tst_program(program, [1, 2, 3]) @unittest.skip("disable") @@ -103,7 +125,7 @@ class GeneralTestCases(FHDLTestCase): "addi 5, 0, 0x12", "stb 5, 5(2)", "ld 5, 0(2)"] - with Program(lst) as program: + with Program(lst, bigendian) as program: self.run_tst_program(program, [1, 2, 3, 4, 5]) @unittest.skip("disable") @@ -113,7 +135,7 @@ class GeneralTestCases(FHDLTestCase): "subf 3, 1, 2", "subfic 4, 1, 0x1337", "neg 5, 1"] - with Program(lst) as program: + with Program(lst, bigendian) as program: self.run_tst_program(program, [1, 2, 3, 4, 5]) @unittest.skip("disable") @@ -125,7 +147,7 @@ class GeneralTestCases(FHDLTestCase): "addc 3, 2, 1", "addi 3, 3, 1" ] - with Program(lst) as program: + with Program(lst, bigendian) as program: self.run_tst_program(program, [1, 2, 3]) @unittest.skip("disable") @@ -133,7 +155,7 @@ class GeneralTestCases(FHDLTestCase): lst = ["addi 1, 0, 0x0FFF", "addis 1, 1, 0x0F" ] - with Program(lst) as program: + with Program(lst, bigendian) as program: self.run_tst_program(program, [1]) @unittest.skip("broken") @@ -141,7 +163,7 @@ class GeneralTestCases(FHDLTestCase): lst = ["addi 1, 0, 3", "mulli 1, 1, 2" ] - with Program(lst) as program: + with Program(lst, bigendian) as program: self.run_tst_program(program, [1]) @unittest.skip("disable") @@ -160,7 +182,7 @@ class GeneralTestCases(FHDLTestCase): 0x1008: (0xabcdef0187654321, 8), 0x1020: (0x1828384822324252, 8), } - with Program(lst) as program: + with Program(lst, bigendian) as program: self.run_tst_program(program, [3,4], initial_mem) @unittest.skip("disable") @@ -178,7 +200,7 @@ class GeneralTestCases(FHDLTestCase): 0x1008: (0xabcdef0187654321, 8), 0x1020: (0x1828384822324252, 8), } - with Program(lst) as program: + with Program(lst, bigendian) as program: self.run_tst_program(program, [1,2,3,4], initial_mem) def test_loop(self): @@ -196,9 +218,16 @@ class GeneralTestCases(FHDLTestCase): "cmpi 0,1,9,12", # compare 9 to value 0, store in CR2 "bc 4,0,-8" # branch if CR2 "test was != 0" ] - with Program(lst) as program: + with Program(lst, bigendian) as program: self.run_tst_program(program, [9], initial_mem={}) + def test_30_addis(self): + lst = [#"addi 0, 0, 5", + "addis 12, 0, 0", + ] + with Program(lst, bigendian) as program: + self.run_tst_program(program, [12]) + def run_tst_program(self, prog, initial_regs=None, initial_sprs=None, initial_mem=None): initial_regs = [0] * 32 @@ -209,7 +238,7 @@ class GeneralTestCases(FHDLTestCase): class DecoderBase: - def run_tst(self, generator, initial_mem=None): + def run_tst(self, generator, initial_mem=None, initial_pc=0): m = Module() comb = m.d.comb @@ -220,13 +249,21 @@ class DecoderBase: pdecode = create_pdecode() m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode) + # place program at requested address + gen = (initial_pc, gen) + simulator = ISA(pdecode2, [0] * 32, {}, 0, initial_mem, 0, initial_insns=gen, respect_pc=True, - disassembly=insn_code) + disassembly=insn_code, + initial_pc=initial_pc, + bigendian=bigendian) sim = Simulator(m) def process(): + #yield pdecode2.dec.bigendian.eq(bigendian) + yield Settle() + while True: try: yield from simulator.setup_one() @@ -244,13 +281,16 @@ class DecoderBase: return simulator - def run_tst_program(self, prog, reglist, initial_mem=None): + def run_tst_program(self, prog, reglist, initial_mem=None, + extra_break_addr=None): import sys - simulator = self.run_tst(prog, initial_mem=initial_mem) + simulator = self.run_tst(prog, initial_mem=initial_mem, + initial_pc=0x20000000) prog.reset() - with run_program(prog, initial_mem) as q: + with run_program(prog, initial_mem, extra_break_addr, + bigendian=bigendian) as q: self.qemu_register_compare(simulator, q, reglist) - self.qemu_mem_compare(simulator, q, reglist) + self.qemu_mem_compare(simulator, q, True) print(simulator.gpr.dump()) def qemu_mem_compare(self, sim, qemu, check=True): @@ -280,14 +320,17 @@ class DecoderBase: print("qemu pc", hex(qpc)) print("qemu cr", hex(qcr)) print("qemu xer", bin(qxer)) + print("sim nia", hex(sim.pc.NIA.value)) print("sim pc", hex(sim.pc.CIA.value)) print("sim cr", hex(sim_cr)) print("sim xer", hex(sim_xer)) - self.assertEqual(qcr, sim_cr) + self.assertEqual(qpc, sim_pc) for reg in regs: qemu_val = qemu.get_register(reg) sim_val = sim.gpr(reg).value - self.assertEqual(qemu_val, sim_val) + self.assertEqual(qemu_val, sim_val, + "expect %x got %x" % (qemu_val, sim_val)) + self.assertEqual(qcr, sim_cr) class DecoderTestCase(DecoderBase, GeneralTestCases):