X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fspec%2Fpinfunctions.py;h=d93f82a9769d3b46241621b878ae9c4f6c766445;hb=303ac486f3db396cf6406e2d40932444a221b9e8;hp=9931ebc66989502341cef82abd07b98b44c1ea1a;hpb=116e8b2aff3e45797321038cb8af32779f122c84;p=pinmux.git diff --git a/src/spec/pinfunctions.py b/src/spec/pinfunctions.py index 9931ebc..d93f82a 100644 --- a/src/spec/pinfunctions.py +++ b/src/spec/pinfunctions.py @@ -37,8 +37,12 @@ sdmmc is never going to do anything other than switch this entire bank all at once. so in this particular example, sdmmc returns: - (['CMD+', 'CLK+', 'D0*', 'D1*', 'D2*', 'D3*'] # pin names - ['D0*', 'D1*', 'D2*', 'D3*']) # ganged bus names + (['CMD+', 'CLK+', 'D0*', 'D1*', 'D2*', 'D3*'] # pin names + ['D0*', 'D1*', 'D2*', 'D3*']) # ganged bus names + + addition: + + 3rd item in list gives the name of the clock. """ @@ -47,64 +51,100 @@ def i2s(suffix, bank): []) +# XXX TODO: correct these. this is a stub for now +# https://bugs.libre-soc.org/show_bug.cgi?id=303 +def lpc(suffix, bank, pincount=4): + lpcpins = ['CMD*', 'CLK+'] + inout = [] + for i in range(pincount): + pname = "D%d*" % i + lpcpins.append(pname) + inout.append(pname) + return (lpcpins, inout, 'CLK') + + def emmc(suffix, bank, pincount=8): - emmcpins = ['CMD+', 'CLK+'] + emmcpins = ['CMD*', 'CLK+'] inout = [] for i in range(pincount): pname = "D%d*" % i emmcpins.append(pname) inout.append(pname) - return (emmcpins, inout) + return (emmcpins, inout, 'CLK') def sdmmc(suffix, bank): return emmc(suffix, bank, pincount=4) +def nspi(suffix, bank, iosize, masteronly=True): + if masteronly: + qpins = ['CK+', 'NSS+'] + else: + qpins = ['CK*', 'NSS*'] + inout = [] + if iosize == 2: + qpins += ['MOSI+', 'MISO-'] + else: + for i in range(iosize): + pname = "IO%d*" % i + qpins.append(pname) + inout.append(pname) + return (qpins, inout, 'CK') + + +def mspi(suffix, bank): + return nspi(suffix, bank, 2, masteronly=True) + + +def mquadspi(suffix, bank): + return nspi(suffix, bank, 4, masteronly=True) + + def spi(suffix, bank): - pins = ['CLK*', 'NSS*', 'MOSI*', 'MISO*'] - return (pins, []) + return nspi(suffix, bank, 2) def quadspi(suffix, bank): - qpins = ['CK*', 'NSS*'] - inout = [] - for i in range(4): - pname = "IO%d*" % i - qpins.append(pname) - inout.append(pname) - return (qpins, inout) + return nspi(suffix, bank, 4) def i2c(suffix, bank): - return (['SDA*', 'SCL*'], []) + """bi-directional (reversible, master-slave) I2C + """ + return (['SDA*', 'SCL*'], [], 'SCL') + + +def mi2c(suffix, bank): + """master-only I2C (clock is output only) + """ + return (['SDA*', 'SCL+'], [], 'SCL') def jtag(suffix, bank): - return (['TMS+', 'TDI-', 'TDO+', 'TCK+'], []) + return (['TMS-', 'TDI-', 'TDO+', 'TCK+'], [], 'TCK') def uart(suffix, bank): - return (['TX+', 'RX-'], []) + return (['TX+', 'RX-'], [], None) def ulpi(suffix, bank): ulpipins = ['CK+', 'DIR+', 'STP+', 'NXT+'] for i in range(8): ulpipins.append('D%d*' % i) - return (ulpipins, []) + return (ulpipins, [], 'CK') def uartfull(suffix, bank): - return (['TX+', 'RX-', 'CTS-', 'RTS+'], - []) + return (['TX+', 'RX-', 'CTS-', 'RTS+'], [], None) def rgbttl(suffix, bank): ttlpins = ['CK+', 'DE+', 'HS+', 'VS+'] for i in range(24): - ttlpins.append("D%d+" % i) - return (ttlpins, []) + ttlpins.append("OUT%d+" % i) + return (ttlpins, [], 'CK') def rgmii(suffix, bank): @@ -117,7 +157,7 @@ def rgmii(suffix, bank): 'EMDC+', 'EMDIO*', 'ETXEN+', 'ETXCK+', 'ECRS-', 'ECOL+', 'ETXERR+'] - return (buspins, []) + return (buspins, [], ['ERXCK', 'ETXCK']) def flexbus1(suffix, bank): @@ -129,73 +169,90 @@ def flexbus1(suffix, bank): inout.append(pname) for i in range(2): buspins.append("CS%d+" % i) - buspins += ['ALE', 'OE', 'RW', 'TA', 'CLK+', - 'A0', 'A1', 'TS', 'TBST', - 'TSIZ0', 'TSIZ1'] + buspins += ['ALE+', 'OE+', 'RW+', 'TA-', + # 'TS+', commented out for now, mirrors ALE, for mux'd mode + 'TBST+', + 'TSIZ0+', 'TSIZ1+'] for i in range(4): - buspins.append("BWE%d" % i) + buspins.append("BWE%d+" % i) for i in range(2, 6): buspins.append("CS%d+" % i) - return (buspins, inout) + return (buspins, inout, None) def flexbus2(suffix, bank): buspins = [] for i in range(8, 32): buspins.append("AD%d*" % i) - return (buspins, buspins) + return (buspins, buspins, None) -def sdram1(suffix, bank): +def sdram1(suffix, bank, n_adr=10): buspins = [] inout = [] - for i in range(16): - pname = "SDRDQM%d*" % i + for i in range(1): + pname = "DQM%d+" % i buspins.append(pname) - inout.append(pname) - for i in range(12): - buspins.append("SDRAD%d+" % i) for i in range(8): - buspins.append("SDRDQ%d+" % i) - for i in range(3): - buspins.append("SDRCS%d#+" % i) - for i in range(2): - buspins.append("SDRDQ%d+" % i) + pname = "D%d*" % i + buspins.append(pname) + inout.append(pname) + for i in range(n_adr): + buspins.append("AD%d+" % i) for i in range(2): - buspins.append("SDRBA%d+" % i) - buspins += ['SDRCKE+', 'SDRRAS#+', 'SDRCAS#+', 'SDRWE#+', - 'SDRRST+'] - return (buspins, inout) + buspins.append("BA%d+" % i) + buspins += ['CLK+', 'CKE+', 'RASn+', 'CASn+', 'WEn+', + 'CSn0+'] + return (buspins, inout, 'CLK') def sdram2(suffix, bank): buspins = [] inout = [] - for i in range(3, 6): - buspins.append("SDRCS%d#+" % i) - for i in range(16, 32): - pname = "SDRDQM%d*" % i + for i in range(10, 13): + buspins.append("AD%d+" % i) + for i in range(1, 2): + pname = "DQM%d+" % i + buspins.append(pname) + for i in range(8, 16): + pname = "D%d*" % i + buspins.append(pname) + inout.append(pname) + return (buspins, inout, None) + + +def sdram3(suffix, bank): + buspins = [] + inout = [] + for i in range(1, 6): + buspins.append("CSn%d+" % i) + for i in range(13, 14): + buspins.append("AD%d+" % i) + for i in range(1, 4): + pname = "DQM%d+" % i + for i in range(8, 32): + pname = "D%d*" % i buspins.append(pname) inout.append(pname) - return (buspins, inout) + return (buspins, inout, None) def mcu8080(suffix, bank): buspins = [] inout = [] for i in range(8): - pname = "MCUD%d*" % i + pname = "D%d*" % i buspins.append(pname) inout.append(pname) for i in range(8): - buspins.append("MCUAD%d+" % (i + 8)) + buspins.append("AD%d+" % (i + 8)) for i in range(6): - buspins.append("MCUCS%d+" % i) + buspins.append("CS%d+" % i) for i in range(2): - buspins.append("MCUNRB%d+" % i) - buspins += ['MCUCD+', 'MCURD+', 'MCUWR+', 'MCUCLE+', 'MCUALE+', - 'MCURST+'] - return (buspins, inout) + buspins.append("NRB%d+" % i) + buspins += ['CD+', 'RD+', 'WR+', 'CLE+', 'ALE+', + 'RST+'] + return (buspins, inout, None) class RangePin(object): @@ -211,25 +268,42 @@ class RangePin(object): def eint(suffix, bank): - return (RangePin("-"), []) + return (RangePin("-"), [], None) def pwm(suffix, bank): - return (RangePin("+"), []) + return (RangePin("+"), [], None) def gpio(suffix, bank): - return (("GPIO%s" % bank, RangePin(prefix=bank, suffix="*")), []) + return (("GPIO%s" % bank, RangePin(prefix=bank, suffix="*")), [], None) + +def vss(suffix, bank): + return (RangePin("-"), [], None) + +def vdd(suffix, bank): + return (RangePin("-"), [], None) +def sys(suffix, bank): + return (['PLLCLK-', # incoming clock (to PLL) + 'PLLSELA0-', 'PLLSELA1-', # PLL divider-selector + 'PLLTESTOUT+', # divided-output (for testing) + 'PLLVCOUT+', # PLL VCO analog out (for testing) + 'RST-', # reset line + ], [], 'CLK') # list functions by name here pinspec = (('IIS', i2s), - ('MMC', emmc), + ('LPC', lpc), + ('EMMC', emmc), ('SD', sdmmc), + ('MSPI', mspi), + ('MQSPI', mquadspi), ('SPI', spi), ('QSPI', quadspi), ('TWI', i2c), + ('MTWI', mi2c), ('JTAG', jtag), ('UART', uart), ('QUART', uartfull), @@ -240,6 +314,10 @@ pinspec = (('IIS', i2s), ('FB', flexbus2), ('SDR', sdram1), ('SDR', sdram2), + ('SDR', sdram3), + ('VSS', vss), + ('VDD', vdd), + ('SYS', sys), ('EINT', eint), ('PWM', pwm), ('GPIO', gpio),