X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fspec%2Fsimple_gpio.py;h=9f7ea89f261e19fbdc5e04a7be1755e56da33908;hb=3c26e7d042c956c0ff7791b78e19b12a3b6e71ad;hp=63beee7f52a2f1b92d77151d90b591af6947cdcb;hpb=0667a5c5183bed2be5ca2c07b2540f7dee32f182;p=pinmux.git diff --git a/src/spec/simple_gpio.py b/src/spec/simple_gpio.py index 63beee7..9f7ea89 100644 --- a/src/spec/simple_gpio.py +++ b/src/spec/simple_gpio.py @@ -7,7 +7,7 @@ Modified for use with pinmux, will probably change the class name later. """ from random import randint from math import ceil, floor -from nmigen import Elaboratable, Module, Signal, Record, Array, Cat +from nmigen import Elaboratable, Module, Signal, Record, Array, Cat, Const from nmigen.hdl.rec import Layout from nmigen.utils import log2_int from nmigen.cli import rtlil @@ -15,6 +15,8 @@ from soc.minerva.wishbone import make_wb_layout from nmutil.util import wrap from soc.bus.test.wb_rw import wb_read, wb_write +from nmutil.gtkw import write_gtkw + cxxsim = False if cxxsim: from nmigen.sim.cxxsim import Simulator, Settle @@ -43,10 +45,11 @@ gpio_layout = (("i", 1), class SimpleGPIO(Elaboratable): def __init__(self, wordsize=4, n_gpio=16): - print("SimpleGPIO: WB Data # of bytes: {0}, # of GPIOs: {1}" - .format(wordsize, n_gpio)) self.wordsize = wordsize self.n_gpio = n_gpio + self.n_rows = ceil(self.n_gpio / self.wordsize) + print("SimpleGPIO: WB Data # of bytes: {0}, #GPIOs: {1}, Rows: {2}" + .format(self.wordsize, self.n_gpio, self.n_rows)) class Spec: pass spec = Spec() spec.addr_wid = 30 @@ -54,18 +57,10 @@ class SimpleGPIO(Elaboratable): spec.reg_wid = wordsize*8 # 32 self.bus = Record(make_wb_layout(spec), name="gpio_wb") - print("CSRBUS layout: ", csrbus_layout) - # create array - probably a cleaner way to do this... - temp = [] - for i in range(self.wordsize): - temp_str = "word{}".format(i) - temp.append(Record(name=temp_str, layout=csrbus_layout)) - self.multicsrbus = Array(temp) - temp = [] for i in range(self.n_gpio): - temp_str = "gpio{}".format(i) - temp.append(Record(name=temp_str, layout=gpio_layout)) + name = "gpio{}".format(i) + temp.append(Record(name=name, layout=gpio_layout)) self.gpio_ports = Array(temp) def elaborate(self, platform): @@ -78,72 +73,100 @@ class SimpleGPIO(Elaboratable): wb_ack = bus.ack gpio_ports = self.gpio_ports - multi = self.multicsrbus - comb += wb_ack.eq(0) + # MultiCSR read and write buses + rd_multi = [] + for i in range(self.wordsize): + name = "rd_word%d" % i + rd_multi.append(Record(name=name, layout=csrbus_layout)) + + wr_multi = [] + for i in range(self.wordsize): + name = "wr_word%d" % i + wr_multi.append(Record(name=name, layout=csrbus_layout)) + + # Combinatorial data reformarting for ease of connection + # Split the WB data into bytes for use with individual GPIOs + comb += Cat(*wr_multi).eq(wb_wr_data) + comb += wb_rd_data.eq(Cat(*rd_multi)) - row_start = Signal(log2_int(self.n_gpio)) # Flag for indicating rd/wr transactions new_transaction = Signal(1) - #print("Types:") - #print("gpio_addr: ", type(gpio_addr)) - # One address used to configure CSR, set output, read input with m.If(bus.cyc & bus.stb): - comb += wb_ack.eq(1) # always ack - # Probably wasteful - sync += row_start.eq(bus.adr * self.wordsize) sync += new_transaction.eq(1) + with m.If(bus.we): # write - # Configure CSR - for byte in range(0, self.wordsize): - sync += multi[byte].eq(wb_wr_data[byte*8:8+byte*8]) - with m.Else(): # read - # Concatinate the GPIO configs that are on the same "row" or - # address and send - multi_cat = [] - for i in range(0, self.wordsize): - multi_cat.append(multi[i]) - comb += wb_rd_data.eq(Cat(multi_cat)) + sync += wb_ack.eq(1) # always ack, always delayed + with m.Else(): + # Update the read multi bus with current GPIO configs + # not ack'ing as we need to wait 1 clk cycle before data ready + for i in range(len(bus.sel)): + GPIO_num = Signal(16) # fixed for now + comb += GPIO_num.eq(bus.adr*len(bus.sel)+i) + with m.If(bus.sel[i]): + sync += rd_multi[i].oe.eq(gpio_ports[GPIO_num].oe) + sync += rd_multi[i].ie.eq(~gpio_ports[GPIO_num].oe) + sync += rd_multi[i].puen.eq(gpio_ports[GPIO_num].puen) + sync += rd_multi[i].pden.eq(gpio_ports[GPIO_num].pden) + with m.If (gpio_ports[GPIO_num].oe): + sync += rd_multi[i].io.eq(gpio_ports[GPIO_num].o) + with m.Else(): + sync += rd_multi[i].io.eq(gpio_ports[GPIO_num].i) + sync += rd_multi[i].bank.eq(gpio_ports[GPIO_num].bank) + with m.Else(): + sync += rd_multi[i].oe.eq(0) + sync += rd_multi[i].ie.eq(0) + sync += rd_multi[i].puen.eq(0) + sync += rd_multi[i].pden.eq(0) + sync += rd_multi[i].io.eq(0) + sync += rd_multi[i].bank.eq(0) with m.Else(): sync += new_transaction.eq(0) - # Update the state of "io" while no WB transactions - for byte in range(0, self.wordsize): - with m.If(gpio_ports[row_start+byte].oe): - sync += multi[byte].io.eq(gpio_ports[row_start+byte].o) - with m.Else(): - sync += multi[byte].io.eq(gpio_ports[row_start+byte].i) - # Only update GPIOs config if a new transaction happened last cycle - # (read or write). Always lags from multi csrbus by 1 clk cycle, most - # sane way I could think of while using Record(). + sync += wb_ack.eq(0) + + # Delayed from the start of transaction by 1 clk cycle with m.If(new_transaction): - for byte in range(0, self.wordsize): - sync += gpio_ports[row_start+byte].oe.eq(multi[byte].oe) - sync += gpio_ports[row_start+byte].puen.eq(multi[byte].puen) - sync += gpio_ports[row_start+byte].pden.eq(multi[byte].pden) - # Check to prevent output being set if GPIO configured as input - # TODO: No checking is done if ie/oe high together - with m.If(gpio_ports[row_start+byte].oe): - sync += gpio_ports[row_start+byte].o.eq(multi[byte].io) - sync += gpio_ports[row_start+byte].bank.eq(multi[byte].bank) + # Update the GPIO configs with sent parameters + with m.If(bus.we): + for i in range(len(bus.sel)): + GPIO_num = Signal(16) # fixed for now + comb += GPIO_num.eq(bus.adr*len(bus.sel)+i) + with m.If(bus.sel[i]): + sync += gpio_ports[GPIO_num].oe.eq(wr_multi[i].oe) + sync += gpio_ports[GPIO_num].puen.eq(wr_multi[i].puen) + sync += gpio_ports[GPIO_num].pden.eq(wr_multi[i].pden) + with m.If (wr_multi[i].oe): + sync += gpio_ports[GPIO_num].o.eq(wr_multi[i].io) + with m.Else(): + sync += gpio_ports[GPIO_num].o.eq(0) + sync += gpio_ports[GPIO_num].bank.eq(wr_multi[i].bank) + sync += wb_ack.eq(0) # stop ack'ing! + # Copy the GPIO config data in read multi bus to the WB data bus + # Ack as we're done + with m.Else(): + sync += wb_ack.eq(1) # Delay ack until rd data is ready! return m def __iter__(self): for field in self.bus.fields.values(): yield field - #yield self.gpio_o + for gpio in range(len(self.gpio_ports)): + for field in self.gpio_ports[gpio].fields.values(): + yield field def ports(self): return list(self) +""" def gpio_test_in_pattern(dut, pattern): num_gpios = len(dut.gpio_ports) print("Test pattern:") print(pattern) for pat in range(0, len(pattern)): for gpio in range(0, num_gpios): - yield from gpio_set_in_pad(dut, gpio, pattern[pat]) + yield gpio_set_in_pad(dut, gpio, pattern[pat]) yield temp = yield from gpio_rd_input(dut, gpio) print("Pattern: {0}, Reading {1}".format(pattern[pat], temp)) @@ -151,6 +174,7 @@ def gpio_test_in_pattern(dut, pattern): pat += 1 if pat == len(pattern): break +""" def test_gpio_single(dut, gpio, use_random=True): oe = 1 @@ -173,30 +197,47 @@ def test_gpio_single(dut, gpio, use_random=True): # Shadow reg container class class GPIOConfigReg(): - def __init__(self): + def __init__(self, shift_dict): + self.shift_dict = shift_dict self.oe=0 self.ie=0 self.puen=0 self.pden=0 self.io=0 self.bank=0 + self.packed=0 - def set(self, oe=0, ie=0, puen=0, pden=0, outval=0, bank=0): + def set(self, oe=0, ie=0, puen=0, pden=0, io=0, bank=0): self.oe=oe self.ie=ie self.puen=puen self.pden=pden - self.io=outval + self.io=io self.bank=bank + self.pack() # Produce packed byte for sending def set_out(self, outval): self.io=outval + self.pack() # Produce packed byte for sending + + # Take config parameters of specified GPIOs, and combine them to produce + # bytes for sending via WB bus + def pack(self): + self.packed = ((self.oe << self.shift_dict['oe']) + | (self.ie << self.shift_dict['ie']) + | (self.puen << self.shift_dict['puen']) + | (self.pden << self.shift_dict['pden']) + | (self.io << self.shift_dict['io']) + | (self.bank << self.shift_dict['bank'])) + + #print("GPIO Packed CSR: {0:x}".format(self.packed)) # Object for storing each gpio's config state class GPIOManager(): - def __init__(self, dut, layout): + def __init__(self, dut, layout, wb_bus): self.dut = dut + self.wb_bus = wb_bus # arrangement of config bits making up csr word self.csr_layout = layout self.shift_dict = self._create_shift_dict() @@ -209,7 +250,15 @@ class GPIOManager(): self.n_rows = ceil(self.n_gpios / self.wordsize) self.shadow_csr = [] for i in range(self.n_gpios): - self.shadow_csr.append(GPIOConfigReg()) + self.shadow_csr.append(GPIOConfigReg(self.shift_dict)) + + def print_info(self): + print("----------") + print("GPIO Block Info:") + print("Number of GPIOs: {}".format(self.n_gpios)) + print("WB Data bus width (in bytes): {}".format(self.wordsize)) + print("Number of rows: {}".format(self.n_rows)) + print("----------") # The shifting of control bits in the configuration word is dependent on the # defined layout. To prevent maintaining the shift constants in a separate @@ -242,81 +291,81 @@ class GPIOManager(): if start >= self.n_gpios: raise Exception("GPIO must be less/equal to last GPIO.") end = start + 1 - print("Setting config for GPIOs {0} until {1}".format(start, end)) + print("Parsed GPIOs {0} until {1}".format(start, end)) return start, end - # Take config parameters of specified GPIOs, and combine them to produce - # bytes for sending via WB bus - def _pack_csr(self, start, end): - #start, end = self._parse_gpio_arg(gpio_str) - num_csr = end-start - csr = [0] * num_csr - for i in range(0, num_csr): - gpio = i + start - print("Pack: gpio{}".format(gpio)) - csr[i] = ((self.shadow_csr[gpio].oe << self.shift_dict['oe']) - | (self.shadow_csr[gpio].ie << self.shift_dict['ie']) - | (self.shadow_csr[gpio].puen << self.shift_dict['puen']) - | (self.shadow_csr[gpio].pden << self.shift_dict['pden']) - | (self.shadow_csr[gpio].io << self.shift_dict['io']) - | (self.shadow_csr[gpio].bank << self.shift_dict['bank'])) - - print("GPIO{0} Packed CSR: {1:x}".format(gpio, csr[i])) - - return csr # return the config byte list + # Take a combined word and update shadow reg's + # TODO: convert hard-coded sizes to use the csrbus_layout (or dict?) + def update_single_shadow(self, csr_byte, gpio): + oe = (csr_byte >> self.shift_dict['oe']) & 0x1 + ie = (csr_byte >> self.shift_dict['ie']) & 0x1 + puen = (csr_byte >> self.shift_dict['puen']) & 0x1 + pden = (csr_byte >> self.shift_dict['pden']) & 0x1 + io = (csr_byte >> self.shift_dict['io']) & 0x1 + bank = (csr_byte >> self.shift_dict['bank']) & 0x3 + + print("csr={0:x} | oe={1}, ie={2}, puen={3}, pden={4}, io={5}, bank={6}" + .format(csr_byte, oe, ie, puen, pden, io, bank)) + + self.shadow_csr[gpio].set(oe, ie, puen, pden, io, bank) + return oe, ie, puen, pden, io, bank def rd_csr(self, row_start): - row_word = yield from wb_read(self.dut.bus, row_start) + row_word = yield from wb_read(self.wb_bus, row_start) print("Returned CSR: {0:x}".format(row_word)) return row_word - def rd_input(self, row_start): - in_val = yield from wb_read(dut.bus, gpio) - in_val = (in_val >> IOSHIFT) & 1 - print("GPIO{0} | Input: {1:b}".format(gpio, in_val)) - return in_val + # Update a single row of configuration registers + def wr_row(self, row_addr, check=False): + curr_gpio = row_addr * self.wordsize + config_word = 0 + for byte in range(0, self.wordsize): + if curr_gpio >= self.n_gpios: + break + config_word += self.shadow_csr[curr_gpio].packed << (8 * byte) + #print("Reading GPIO{} shadow reg".format(curr_gpio)) + curr_gpio += 1 + print("Writing shadow CSRs val {0:x} to row addr {1:x}" + .format(config_word, row_addr)) + yield from wb_write(self.wb_bus, row_addr, config_word) + yield # Allow one clk cycle to propagate - def print_info(self): - print("----------") - print("GPIO Block Info:") - print("Number of GPIOs: {}".format(self.n_gpios)) - print("WB Data bus width (in bytes): {}".format(self.wordsize)) - print("Number of rows: {}".format(self.n_rows)) - print("----------") + if(check): + read_word = yield from self.rd_row(row_addr) + assert config_word == read_word + + # Read a single address row of GPIO CSRs, and update shadow + def rd_row(self, row_addr): + read_word = yield from self.rd_csr(row_addr) + curr_gpio = row_addr * self.wordsize + single_csr = 0 + for byte in range(0, self.wordsize): + if curr_gpio >= self.n_gpios: + break + single_csr = (read_word >> (8 * byte)) & 0xFF + #print("Updating GPIO{0} shadow reg to {1:x}" + # .format(curr_gpio, single_csr)) + self.update_single_shadow(single_csr, curr_gpio) + curr_gpio += 1 + return read_word # Write all shadow registers to GPIO block - def wr_all(self): - # UPDATE using ALL shadow registers - csr = self._pack_csr(0, self.n_gpios) - #start_addr = floor(start / self.wordsize) - start_addr = 0 - curr_gpio = 0 + def wr_all(self, check=False): for row in range(0, self.n_rows): - row_word = 0 - start_byte = curr_gpio % self.wordsize - for byte in range(start_byte, self.wordsize): - if curr_gpio > self.n_gpios: - break - #row_word += csr[byte] << (8 * byte) - row_word += csr[curr_gpio] << (8 * byte) - curr_gpio += 1 - print("Configuring CSR to {0:x} to addr: {1:x}" - .format(row_word, start_addr+row)) - yield from wb_write(self.dut.bus, start_addr+row, row_word) - yield # Allow one clk cycle to propagate - - if(True): #check): - test_row = yield from self.rd_csr(start_addr+row) - assert row_word == test_row + yield from self.wr_row(row, check) + # Read all GPIO block row addresses and update shadow reg's + def rd_all(self, check=False): + for row in range(0, self.n_rows): + yield from self.rd_row(row, check) def config(self, gpio_str, oe, ie, puen, pden, outval, bank, check=False): start, end = self._parse_gpio_arg(gpio_str) # Update the shadow configuration for gpio in range(start, end): - print(oe, ie, puen, pden, outval, bank) + # print(oe, ie, puen, pden, outval, bank) self.shadow_csr[gpio].set(oe, ie, puen, pden, outval, bank) - + # TODO: only update the required rows? yield from self.wr_all() # Set/Clear the output bit for single or group of GPIOs @@ -332,29 +381,52 @@ class GPIOManager(): .format(start, end-1, outval)) yield from self.wr_all() - """ - # Not used normally - only for debug - def reg_write(dut, gpio, reg_val): - print("Configuring CSR to {0:x}".format(reg_val)) - yield from wb_write(dut.bus, gpio, reg_val) + + def rd_input(self, gpio_str): # REWORK + start, end = self._parse_gpio_arg(gpio_str) + curr_gpio = 0 + # Too difficult to think about, just read all configs + #start_row = floor(start / self.wordsize) + # Hack because end corresponds to range limit, but maybe on same row + # TODO: clean + #end_row = floor( (end-1) / self.wordsize) + 1 + read_data = [0] * self.n_rows + for row in range(0, self.n_rows): + read_data[row] = yield from self.rd_row(row) + + num_to_read = (end - start) + read_in = [0] * num_to_read + curr_gpio = 0 + for i in range(0, num_to_read): + read_in[i] = self.shadow_csr[curr_gpio].io + curr_gpio += 1 + + print("GPIOs {0} until {1}, i={2}".format(start, end, read_in)) + return read_in # TODO: There's probably a cleaner way to clear the bit... - def gpio_set_in_pad(dut, gpio, in_val): - old_in_val = yield dut.gpio_i - if in_val: - new_in_val = old_in_val | (in_val << gpio) - else: - temp = (old_in_val >> gpio) & 1 - if temp: - mask = ~(1 << gpio) - new_in_val = old_in_val & mask - else: - new_in_val = old_in_val - print("Previous GPIO i: {0:b} | New GPIO i: {1:b}" - .format(old_in_val, new_in_val)) - yield dut.gpio_i.eq(new_in_val) - yield # Allow one clk cycle to propagate - """ + def sim_set_in_pad(self, gpio_str, in_val): + start, end = self._parse_gpio_arg(gpio_str) + for gpio in range(start, end): + old_in_val = yield self.dut.gpio_ports[gpio].i + print(old_in_val) + print("GPIO{0} Previous i: {1:b} | New i: {2:b}" + .format(gpio, old_in_val, in_val)) + yield self.dut.gpio_ports[gpio].i.eq(in_val) + yield # Allow one clk cycle to propagate + + def rd_shadow(self): + shadow_csr = [0] * self.n_gpios + for gpio in range(0, self.n_gpios): + shadow_csr[gpio] = self.shadow_csr[gpio].packed + + hex_str = "" + for reg in shadow_csr: + hex_str += " "+hex(reg) + print("Shadow reg's: ", hex_str) + + return shadow_csr + def sim_gpio(dut, use_random=True): #print(dut) @@ -380,12 +452,96 @@ def sim_gpio(dut, use_random=True): #print("CSR Val: {0:x}".format(csr_val)) print("Finished the simple GPIO block test!") +def gen_gtkw_doc(n_gpios, wordsize, filename): + # GTKWave doc generation + wb_data_width = wordsize*8 + n_rows = ceil(n_gpios/wordsize) + style = { + '': {'base': 'hex'}, + 'in': {'color': 'orange'}, + 'out': {'color': 'yellow'}, + 'debug': {'module': 'top', 'color': 'red'} + } + + # Create a trace list, each block expected to be a tuple() + traces = [] + wb_traces = ('Wishbone Bus', [ + ('gpio_wb__cyc', 'in'), + ('gpio_wb__stb', 'in'), + ('gpio_wb__we', 'in'), + ('gpio_wb__adr[27:0]', 'in'), + ('gpio_wb__sel[3:0]', 'in'), + ('gpio_wb__dat_w[{}:0]'.format(wb_data_width-1), 'in'), + ('gpio_wb__dat_r[{}:0]'.format(wb_data_width-1), 'out'), + ('gpio_wb__ack', 'out'), + ]) + traces.append(wb_traces) + + gpio_internal_traces = ('Internal', [ + ('clk', 'in'), + ('new_transaction'), + ('rst', 'in') + ]) + traces.append(gpio_internal_traces) + + traces.append({'comment': 'Multi-byte GPIO config read bus'}) + for word in range(0, wordsize): + prefix = "rd_word{}__".format(word) + single_word = [] + word_signals = [] + single_word.append('Word{}'.format(word)) + word_signals.append((prefix+'bank[{}:0]'.format(NUMBANKBITS-1))) + word_signals.append((prefix+'ie')) + word_signals.append((prefix+'io')) + word_signals.append((prefix+'oe')) + word_signals.append((prefix+'pden')) + word_signals.append((prefix+'puen')) + single_word.append(word_signals) + traces.append(tuple(single_word)) + + traces.append({'comment': 'Multi-byte GPIO config write bus'}) + for word in range(0, wordsize): + prefix = "wr_word{}__".format(word) + single_word = [] + word_signals = [] + single_word.append('Word{}'.format(word)) + word_signals.append((prefix+'bank[{}:0]'.format(NUMBANKBITS-1))) + word_signals.append((prefix+'ie')) + word_signals.append((prefix+'io')) + word_signals.append((prefix+'oe')) + word_signals.append((prefix+'pden')) + word_signals.append((prefix+'puen')) + single_word.append(word_signals) + traces.append(tuple(single_word)) + + for gpio in range(0, n_gpios): + prefix = "gpio{}__".format(gpio) + single_gpio = [] + gpio_signals = [] + single_gpio.append('GPIO{} Port'.format(gpio)) + gpio_signals.append((prefix+'bank[{}:0]'.format(NUMBANKBITS-1), 'out')) + gpio_signals.append( (prefix+'i', 'in') ) + gpio_signals.append( (prefix+'o', 'out') ) + gpio_signals.append( (prefix+'oe', 'out') ) + gpio_signals.append( (prefix+'pden', 'out') ) + gpio_signals.append( (prefix+'puen', 'out') ) + single_gpio.append(gpio_signals) + traces.append(tuple(single_gpio)) + + #print(traces) + + #module = "top.xics_icp" + module = "bench.top.xics_icp" + write_gtkw(filename+".gtkw", filename+".vcd", traces, style, + module=module) + def test_gpio(): - num_gpio = 8 + filename = "test_gpio" # Doesn't include extension + n_gpios = 8 wordsize = 4 # Number of bytes in the WB data word - dut = SimpleGPIO(wordsize, num_gpio) + dut = SimpleGPIO(wordsize, n_gpios) vl = rtlil.convert(dut, ports=dut.ports()) - with open("test_gpio.il", "w") as f: + with open(filename+".il", "w") as f: f.write(vl) m = Module() @@ -396,12 +552,15 @@ def test_gpio(): #sim.add_sync_process(wrap(sim_gpio(dut, use_random=False))) sim.add_sync_process(wrap(test_gpioman(dut))) - sim_writer = sim.write_vcd('test_gpio.vcd') + sim_writer = sim.write_vcd(filename+".vcd") with sim_writer: sim.run() + gen_gtkw_doc(n_gpios, wordsize, filename) + def test_gpioman(dut): - gpios = GPIOManager(dut, csrbus_layout) + print("------START----------------------") + gpios = GPIOManager(dut, csrbus_layout, dut.bus) gpios.print_info() #gpios._parse_gpio_arg("all") #gpios._parse_gpio_arg("0") @@ -416,9 +575,15 @@ def test_gpioman(dut): bank = 3 yield from gpios.config("0-3", oe=1, ie=0, puen=0, pden=1, outval=0, bank=2) ie = 1 - yield from gpios.config("4-7", oe=0, ie=1, puen=0, pden=1, outval=0, bank=2) - yield from gpios.set_out("0-3", outval=1) + yield from gpios.config("4-7", oe=0, ie=1, puen=0, pden=1, outval=0, bank=6) + yield from gpios.set_out("0-1", outval=1) + + #yield from gpios.rd_all() + yield from gpios.sim_set_in_pad("6-7", 1) + print("----------------------------") + yield from gpios.rd_input("4-7") + gpios.rd_shadow() if __name__ == '__main__': test_gpio()