X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fvulkan%2Fgen7_pipeline.c;h=80c5f1a99a14a599f5b5b9afb1215afa7879ff37;hb=b1cd025b88e3651fac8dd2f7861516f653422ee4;hp=a5c7a201690ccdad0626b578e786676ba0100e3e;hpb=31af126229a4c2a5a532e43433c57fad263b03af;p=mesa.git diff --git a/src/vulkan/gen7_pipeline.c b/src/vulkan/gen7_pipeline.c index a5c7a201690..80c5f1a99a1 100644 --- a/src/vulkan/gen7_pipeline.c +++ b/src/vulkan/gen7_pipeline.c @@ -29,20 +29,27 @@ #include "anv_private.h" +#include "gen7_pack.h" +#include "gen75_pack.h" + static void gen7_emit_vertex_input(struct anv_pipeline *pipeline, const VkPipelineVertexInputStateCreateInfo *info) { const bool sgvs = pipeline->vs_prog_data.uses_vertexid || pipeline->vs_prog_data.uses_instanceid; - const uint32_t element_count = info->attributeCount + (sgvs ? 1 : 0); + const uint32_t element_count = + info->vertexAttributeDescriptionCount + (sgvs ? 1 : 0); const uint32_t num_dwords = 1 + element_count * 2; uint32_t *p; + if (info->vertexAttributeDescriptionCount == 0 && !sgvs) + return; + p = anv_batch_emitn(&pipeline->batch, num_dwords, GEN7_3DSTATE_VERTEX_ELEMENTS); - for (uint32_t i = 0; i < info->attributeCount; i++) { + for (uint32_t i = 0; i < info->vertexAttributeDescriptionCount; i++) { const VkVertexInputAttributeDescription *desc = &info->pVertexAttributeDescriptions[i]; const struct anv_format *format = anv_format_for_vk_format(desc->format); @@ -52,7 +59,7 @@ gen7_emit_vertex_input(struct anv_pipeline *pipeline, .Valid = true, .SourceElementFormat = format->surface_format, .EdgeFlagEnable = false, - .SourceElementOffset = desc->offsetInBytes, + .SourceElementOffset = desc->offset, .Component0Control = VFCOMP_STORE_SRC, .Component1Control = format->num_channels >= 2 ? VFCOMP_STORE_SRC : VFCOMP_STORE_0, .Component2Control = format->num_channels >= 3 ? VFCOMP_STORE_SRC : VFCOMP_STORE_0, @@ -71,31 +78,31 @@ gen7_emit_vertex_input(struct anv_pipeline *pipeline, .Component2Control = VFCOMP_STORE_VID, .Component3Control = VFCOMP_STORE_IID }; - GEN7_VERTEX_ELEMENT_STATE_pack(NULL, &p[1 + info->attributeCount * 2], &element); + GEN7_VERTEX_ELEMENT_STATE_pack(NULL, &p[1 + info->vertexAttributeDescriptionCount * 2], &element); } } static const uint32_t vk_to_gen_cullmode[] = { [VK_CULL_MODE_NONE] = CULLMODE_NONE, - [VK_CULL_MODE_FRONT] = CULLMODE_FRONT, - [VK_CULL_MODE_BACK] = CULLMODE_BACK, + [VK_CULL_MODE_FRONT_BIT] = CULLMODE_FRONT, + [VK_CULL_MODE_BACK_BIT] = CULLMODE_BACK, [VK_CULL_MODE_FRONT_AND_BACK] = CULLMODE_BOTH }; static const uint32_t vk_to_gen_fillmode[] = { - [VK_FILL_MODE_POINTS] = RASTER_POINT, - [VK_FILL_MODE_WIREFRAME] = RASTER_WIREFRAME, - [VK_FILL_MODE_SOLID] = RASTER_SOLID + [VK_POLYGON_MODE_FILL] = RASTER_SOLID, + [VK_POLYGON_MODE_LINE] = RASTER_WIREFRAME, + [VK_POLYGON_MODE_POINT] = RASTER_POINT, }; static const uint32_t vk_to_gen_front_face[] = { - [VK_FRONT_FACE_CCW] = CounterClockwise, - [VK_FRONT_FACE_CW] = Clockwise + [VK_FRONT_FACE_COUNTER_CLOCKWISE] = 1, + [VK_FRONT_FACE_CLOCKWISE] = 0 }; static void gen7_emit_rs_state(struct anv_pipeline *pipeline, - const VkPipelineRasterStateCreateInfo *info, + const VkPipelineRasterizationStateCreateInfo *info, const struct anv_graphics_pipeline_create_info *extra) { struct GEN7_3DSTATE_SF sf = { @@ -107,8 +114,8 @@ gen7_emit_rs_state(struct anv_pipeline *pipeline, /* LegacyGlobalDepthBiasEnable */ .StatisticsEnable = true, - .FrontFaceFillMode = vk_to_gen_fillmode[info->fillMode], - .BackFaceFillMode = vk_to_gen_fillmode[info->fillMode], + .FrontFaceFillMode = vk_to_gen_fillmode[info->polygonMode], + .BackFaceFillMode = vk_to_gen_fillmode[info->polygonMode], .ViewTransformEnable = !(extra && extra->disable_viewport), .FrontWinding = vk_to_gen_front_face[info->frontFace], /* bool AntiAliasingEnable; */ @@ -138,10 +145,10 @@ static const uint32_t vk_to_gen_compare_op[] = { [VK_COMPARE_OP_NEVER] = PREFILTEROPNEVER, [VK_COMPARE_OP_LESS] = PREFILTEROPLESS, [VK_COMPARE_OP_EQUAL] = PREFILTEROPEQUAL, - [VK_COMPARE_OP_LESS_EQUAL] = PREFILTEROPLEQUAL, + [VK_COMPARE_OP_LESS_OR_EQUAL] = PREFILTEROPLEQUAL, [VK_COMPARE_OP_GREATER] = PREFILTEROPGREATER, [VK_COMPARE_OP_NOT_EQUAL] = PREFILTEROPNOTEQUAL, - [VK_COMPARE_OP_GREATER_EQUAL] = PREFILTEROPGEQUAL, + [VK_COMPARE_OP_GREATER_OR_EQUAL] = PREFILTEROPGEQUAL, [VK_COMPARE_OP_ALWAYS] = PREFILTEROPALWAYS, }; @@ -149,11 +156,11 @@ static const uint32_t vk_to_gen_stencil_op[] = { [VK_STENCIL_OP_KEEP] = STENCILOP_KEEP, [VK_STENCIL_OP_ZERO] = STENCILOP_ZERO, [VK_STENCIL_OP_REPLACE] = STENCILOP_REPLACE, - [VK_STENCIL_OP_INC_CLAMP] = STENCILOP_INCRSAT, - [VK_STENCIL_OP_DEC_CLAMP] = STENCILOP_DECRSAT, + [VK_STENCIL_OP_INCREMENT_AND_CLAMP] = STENCILOP_INCRSAT, + [VK_STENCIL_OP_DECREMENT_AND_CLAMP] = STENCILOP_DECRSAT, [VK_STENCIL_OP_INVERT] = STENCILOP_INVERT, - [VK_STENCIL_OP_INC_WRAP] = STENCILOP_INCR, - [VK_STENCIL_OP_DEC_WRAP] = STENCILOP_DECR, + [VK_STENCIL_OP_INCREMENT_AND_WRAP] = STENCILOP_INCR, + [VK_STENCIL_OP_DECREMENT_AND_WRAP] = STENCILOP_DECR, }; static const uint32_t vk_to_gen_blend_op[] = { @@ -170,11 +177,11 @@ static const uint32_t vk_to_gen_logic_op[] = { [VK_LOGIC_OP_AND] = LOGICOP_AND, [VK_LOGIC_OP_AND_REVERSE] = LOGICOP_AND_REVERSE, [VK_LOGIC_OP_AND_INVERTED] = LOGICOP_AND_INVERTED, - [VK_LOGIC_OP_NOOP] = LOGICOP_NOOP, + [VK_LOGIC_OP_NO_OP] = LOGICOP_NOOP, [VK_LOGIC_OP_XOR] = LOGICOP_XOR, [VK_LOGIC_OP_OR] = LOGICOP_OR, [VK_LOGIC_OP_NOR] = LOGICOP_NOR, - [VK_LOGIC_OP_EQUIV] = LOGICOP_EQUIV, + [VK_LOGIC_OP_EQUIVALENT] = LOGICOP_EQUIV, [VK_LOGIC_OP_INVERT] = LOGICOP_INVERT, [VK_LOGIC_OP_OR_REVERSE] = LOGICOP_OR_REVERSE, [VK_LOGIC_OP_COPY_INVERTED] = LOGICOP_COPY_INVERTED, @@ -184,25 +191,25 @@ static const uint32_t vk_to_gen_logic_op[] = { }; static const uint32_t vk_to_gen_blend[] = { - [VK_BLEND_ZERO] = BLENDFACTOR_ZERO, - [VK_BLEND_ONE] = BLENDFACTOR_ONE, - [VK_BLEND_SRC_COLOR] = BLENDFACTOR_SRC_COLOR, - [VK_BLEND_ONE_MINUS_SRC_COLOR] = BLENDFACTOR_INV_SRC_COLOR, - [VK_BLEND_DEST_COLOR] = BLENDFACTOR_DST_COLOR, - [VK_BLEND_ONE_MINUS_DEST_COLOR] = BLENDFACTOR_INV_DST_COLOR, - [VK_BLEND_SRC_ALPHA] = BLENDFACTOR_SRC_ALPHA, - [VK_BLEND_ONE_MINUS_SRC_ALPHA] = BLENDFACTOR_INV_SRC_ALPHA, - [VK_BLEND_DEST_ALPHA] = BLENDFACTOR_DST_ALPHA, - [VK_BLEND_ONE_MINUS_DEST_ALPHA] = BLENDFACTOR_INV_DST_ALPHA, - [VK_BLEND_CONSTANT_COLOR] = BLENDFACTOR_CONST_COLOR, - [VK_BLEND_ONE_MINUS_CONSTANT_COLOR] = BLENDFACTOR_INV_CONST_COLOR, - [VK_BLEND_CONSTANT_ALPHA] = BLENDFACTOR_CONST_ALPHA, - [VK_BLEND_ONE_MINUS_CONSTANT_ALPHA] = BLENDFACTOR_INV_CONST_ALPHA, - [VK_BLEND_SRC_ALPHA_SATURATE] = BLENDFACTOR_SRC_ALPHA_SATURATE, - [VK_BLEND_SRC1_COLOR] = BLENDFACTOR_SRC1_COLOR, - [VK_BLEND_ONE_MINUS_SRC1_COLOR] = BLENDFACTOR_INV_SRC1_COLOR, - [VK_BLEND_SRC1_ALPHA] = BLENDFACTOR_SRC1_ALPHA, - [VK_BLEND_ONE_MINUS_SRC1_ALPHA] = BLENDFACTOR_INV_SRC1_ALPHA, + [VK_BLEND_FACTOR_ZERO] = BLENDFACTOR_ZERO, + [VK_BLEND_FACTOR_ONE] = BLENDFACTOR_ONE, + [VK_BLEND_FACTOR_SRC_COLOR] = BLENDFACTOR_SRC_COLOR, + [VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR] = BLENDFACTOR_INV_SRC_COLOR, + [VK_BLEND_FACTOR_DST_COLOR] = BLENDFACTOR_DST_COLOR, + [VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR] = BLENDFACTOR_INV_DST_COLOR, + [VK_BLEND_FACTOR_SRC_ALPHA] = BLENDFACTOR_SRC_ALPHA, + [VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA] = BLENDFACTOR_INV_SRC_ALPHA, + [VK_BLEND_FACTOR_DST_ALPHA] = BLENDFACTOR_DST_ALPHA, + [VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA] = BLENDFACTOR_INV_DST_ALPHA, + [VK_BLEND_FACTOR_CONSTANT_COLOR] = BLENDFACTOR_CONST_COLOR, + [VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR] = BLENDFACTOR_INV_CONST_COLOR, + [VK_BLEND_FACTOR_CONSTANT_ALPHA] = BLENDFACTOR_CONST_ALPHA, + [VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA] = BLENDFACTOR_INV_CONST_ALPHA, + [VK_BLEND_FACTOR_SRC_ALPHA_SATURATE] = BLENDFACTOR_SRC_ALPHA_SATURATE, + [VK_BLEND_FACTOR_SRC1_COLOR] = BLENDFACTOR_SRC1_COLOR, + [VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR] = BLENDFACTOR_INV_SRC1_COLOR, + [VK_BLEND_FACTOR_SRC1_ALPHA] = BLENDFACTOR_SRC1_ALPHA, + [VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA] = BLENDFACTOR_INV_SRC1_ALPHA, }; static void @@ -218,114 +225,107 @@ gen7_emit_ds_state(struct anv_pipeline *pipeline, return; } - bool has_stencil = false; /* enable if subpass has stencil? */ - struct GEN7_DEPTH_STENCIL_STATE state = { - /* Is this what we need to do? */ - .StencilBufferWriteEnable = has_stencil, - - .StencilTestEnable = info->stencilTestEnable, - .StencilTestFunction = vk_to_gen_compare_op[info->front.stencilCompareOp], - .StencilFailOp = vk_to_gen_stencil_op[info->front.stencilFailOp], - .StencilPassDepthFailOp = vk_to_gen_stencil_op[info->front.stencilDepthFailOp], - .StencilPassDepthPassOp = vk_to_gen_stencil_op[info->front.stencilPassOp], - - .DoubleSidedStencilEnable = true, - - .BackFaceStencilTestFunction = vk_to_gen_compare_op[info->back.stencilCompareOp], - .BackfaceStencilFailOp = vk_to_gen_stencil_op[info->back.stencilFailOp], - .BackfaceStencilPassDepthFailOp = vk_to_gen_stencil_op[info->back.stencilDepthFailOp], - .BackfaceStencilPassDepthPassOp = vk_to_gen_stencil_op[info->back.stencilPassOp], - .DepthTestEnable = info->depthTestEnable, - .DepthTestFunction = vk_to_gen_compare_op[info->depthCompareOp], .DepthBufferWriteEnable = info->depthWriteEnable, + .DepthTestFunction = vk_to_gen_compare_op[info->depthCompareOp], + .DoubleSidedStencilEnable = true, + + .StencilTestEnable = info->stencilTestEnable, + .StencilFailOp = vk_to_gen_stencil_op[info->front.failOp], + .StencilPassDepthPassOp = vk_to_gen_stencil_op[info->front.passOp], + .StencilPassDepthFailOp = vk_to_gen_stencil_op[info->front.depthFailOp], + .StencilTestFunction = vk_to_gen_compare_op[info->front.compareOp], + + .BackfaceStencilFailOp = vk_to_gen_stencil_op[info->back.failOp], + .BackfaceStencilPassDepthPassOp = vk_to_gen_stencil_op[info->back.passOp], + .BackfaceStencilPassDepthFailOp = vk_to_gen_stencil_op[info->back.depthFailOp], + .BackFaceStencilTestFunction = vk_to_gen_compare_op[info->back.compareOp], }; - + GEN7_DEPTH_STENCIL_STATE_pack(NULL, &pipeline->gen7.depth_stencil_state, &state); } static void gen7_emit_cb_state(struct anv_pipeline *pipeline, - const VkPipelineColorBlendStateCreateInfo *info) + const VkPipelineColorBlendStateCreateInfo *info, + const VkPipelineMultisampleStateCreateInfo *ms_info) { struct anv_device *device = pipeline->device; - /* FIXME-GEN7: All render targets share blend state settings on gen7, we - * can't implement this. - */ - const VkPipelineColorBlendAttachmentState *a = &info->pAttachments[0]; - uint32_t num_dwords = GEN7_BLEND_STATE_length; pipeline->blend_state = anv_state_pool_alloc(&device->dynamic_state_pool, num_dwords * 4, 64); - struct GEN7_BLEND_STATE blend_state = { - .ColorBufferBlendEnable = a->blendEnable, - .IndependentAlphaBlendEnable = true, /* FIXME: yes? */ - .AlphaBlendFunction = vk_to_gen_blend_op[a->blendOpAlpha], - - .SourceAlphaBlendFactor = vk_to_gen_blend[a->srcBlendAlpha], - .DestinationAlphaBlendFactor = vk_to_gen_blend[a->destBlendAlpha], - - .ColorBlendFunction = vk_to_gen_blend_op[a->blendOpColor], - .SourceBlendFactor = vk_to_gen_blend[a->srcBlendColor], - .DestinationBlendFactor = vk_to_gen_blend[a->destBlendColor], - .AlphaToCoverageEnable = info->alphaToCoverageEnable, - -#if 0 - bool AlphaToOneEnable; - bool AlphaToCoverageDitherEnable; -#endif - - .WriteDisableAlpha = !(a->channelWriteMask & VK_CHANNEL_A_BIT), - .WriteDisableRed = !(a->channelWriteMask & VK_CHANNEL_R_BIT), - .WriteDisableGreen = !(a->channelWriteMask & VK_CHANNEL_G_BIT), - .WriteDisableBlue = !(a->channelWriteMask & VK_CHANNEL_B_BIT), - - .LogicOpEnable = info->logicOpEnable, - .LogicOpFunction = vk_to_gen_logic_op[info->logicOp], + if (info->pAttachments == NULL) { + struct GEN7_BLEND_STATE blend_state = { + .ColorBufferBlendEnable = false, + .WriteDisableAlpha = false, + .WriteDisableRed = false, + .WriteDisableGreen = false, + .WriteDisableBlue = false, + }; -#if 0 - bool AlphaTestEnable; - uint32_t AlphaTestFunction; - bool ColorDitherEnable; - uint32_t XDitherOffset; - uint32_t YDitherOffset; - uint32_t ColorClampRange; - bool PreBlendColorClampEnable; - bool PostBlendColorClampEnable; -#endif - }; + GEN7_BLEND_STATE_pack(NULL, pipeline->blend_state.map, &blend_state); + } else { + /* FIXME-GEN7: All render targets share blend state settings on gen7, we + * can't implement this. + */ + const VkPipelineColorBlendAttachmentState *a = &info->pAttachments[0]; + + struct GEN7_BLEND_STATE blend_state = { + .ColorBufferBlendEnable = a->blendEnable, + .IndependentAlphaBlendEnable = true, /* FIXME: yes? */ + .AlphaBlendFunction = vk_to_gen_blend_op[a->alphaBlendOp], + + .SourceAlphaBlendFactor = vk_to_gen_blend[a->srcAlphaBlendFactor], + .DestinationAlphaBlendFactor = vk_to_gen_blend[a->dstAlphaBlendFactor], + + .ColorBlendFunction = vk_to_gen_blend_op[a->colorBlendOp], + .SourceBlendFactor = vk_to_gen_blend[a->srcColorBlendFactor], + .DestinationBlendFactor = vk_to_gen_blend[a->dstColorBlendFactor], + .AlphaToCoverageEnable = ms_info && ms_info->alphaToCoverageEnable, + +# if 0 + bool AlphaToOneEnable; + bool AlphaToCoverageDitherEnable; +# endif + + .WriteDisableAlpha = !(a->colorWriteMask & VK_COLOR_COMPONENT_A_BIT), + .WriteDisableRed = !(a->colorWriteMask & VK_COLOR_COMPONENT_R_BIT), + .WriteDisableGreen = !(a->colorWriteMask & VK_COLOR_COMPONENT_G_BIT), + .WriteDisableBlue = !(a->colorWriteMask & VK_COLOR_COMPONENT_B_BIT), + + .LogicOpEnable = info->logicOpEnable, + .LogicOpFunction = vk_to_gen_logic_op[info->logicOp], + +# if 0 + bool AlphaTestEnable; + uint32_t AlphaTestFunction; + bool ColorDitherEnable; + uint32_t XDitherOffset; + uint32_t YDitherOffset; + uint32_t ColorClampRange; + bool PreBlendColorClampEnable; + bool PostBlendColorClampEnable; +# endif + }; - GEN7_BLEND_STATE_pack(NULL, pipeline->blend_state.map, &blend_state); + GEN7_BLEND_STATE_pack(NULL, pipeline->blend_state.map, &blend_state); + } anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_BLEND_STATE_POINTERS, .BlendStatePointer = pipeline->blend_state.offset); } -static const uint32_t vk_to_gen_primitive_type[] = { - [VK_PRIMITIVE_TOPOLOGY_POINT_LIST] = _3DPRIM_POINTLIST, - [VK_PRIMITIVE_TOPOLOGY_LINE_LIST] = _3DPRIM_LINELIST, - [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP] = _3DPRIM_LINESTRIP, - [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST] = _3DPRIM_TRILIST, - [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP] = _3DPRIM_TRISTRIP, - [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN] = _3DPRIM_TRIFAN, - [VK_PRIMITIVE_TOPOLOGY_LINE_LIST_ADJ] = _3DPRIM_LINELIST_ADJ, - [VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_ADJ] = _3DPRIM_LINESTRIP_ADJ, - [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_ADJ] = _3DPRIM_TRILIST_ADJ, - [VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_ADJ] = _3DPRIM_TRISTRIP_ADJ, - [VK_PRIMITIVE_TOPOLOGY_PATCH] = _3DPRIM_PATCHLIST_1 -}; - static inline uint32_t scratch_space(const struct brw_stage_prog_data *prog_data) { return ffs(prog_data->total_scratch / 1024); } -VkResult -gen7_graphics_pipeline_create( +GENX_FUNC(GEN7, GEN75) VkResult +genX(graphics_pipeline_create)( VkDevice _device, const VkGraphicsPipelineCreateInfo* pCreateInfo, const struct anv_graphics_pipeline_create_info *extra, @@ -351,12 +351,13 @@ gen7_graphics_pipeline_create( assert(pCreateInfo->pVertexInputState); gen7_emit_vertex_input(pipeline, pCreateInfo->pVertexInputState); - assert(pCreateInfo->pRasterState); - gen7_emit_rs_state(pipeline, pCreateInfo->pRasterState, extra); + assert(pCreateInfo->pRasterizationState); + gen7_emit_rs_state(pipeline, pCreateInfo->pRasterizationState, extra); gen7_emit_ds_state(pipeline, pCreateInfo->pDepthStencilState); - gen7_emit_cb_state(pipeline, pCreateInfo->pColorBlendState); + gen7_emit_cb_state(pipeline, pCreateInfo->pColorBlendState, + pCreateInfo->pMultisampleState); anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_VF_STATISTICS, .StatisticsEnable = true); @@ -365,6 +366,19 @@ gen7_graphics_pipeline_create( anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_DS, .DSFunctionEnable = false); anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_STREAMOUT, .SOFunctionEnable = false); + /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1: + * + * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth stall + * needs to be sent just prior to any 3DSTATE_VS, 3DSTATE_URB_VS, + * 3DSTATE_CONSTANT_VS, 3DSTATE_BINDING_TABLE_POINTER_VS, + * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one PIPE_CONTROL + * needs to be sent before any combination of VS associated 3DSTATE." + */ + anv_batch_emit(&pipeline->batch, GEN7_PIPE_CONTROL, + .DepthStallEnable = true, + .PostSyncOperation = WriteImmediateData, + .Address = { &device->workaround_bo, 0 }); + anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_VS, .ConstantBufferOffset = 0, .ConstantBufferSize = 4); @@ -377,7 +391,8 @@ gen7_graphics_pipeline_create( anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_AA_LINE_PARAMETERS); - const VkPipelineRasterStateCreateInfo *rs_info = pCreateInfo->pRasterState; + const VkPipelineRasterizationStateCreateInfo *rs_info = + pCreateInfo->pRasterizationState; anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_CLIP, .FrontWinding = vk_to_gen_front_face[rs_info->frontFace], @@ -448,9 +463,9 @@ gen7_graphics_pipeline_create( #endif if (pipeline->vs_vec4 == NO_KERNEL || (extra && extra->disable_vs)) - anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_VS, .VSFunctionEnable = false); + anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VS), .VSFunctionEnable = false); else - anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_VS, + anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VS), .KernelStartPointer = pipeline->vs_vec4, .ScratchSpaceBaseOffset = pipeline->scratch_start[VK_SHADER_STAGE_VERTEX], .PerThreadScratchSpace = scratch_space(&vue_prog_data->base), @@ -467,12 +482,12 @@ gen7_graphics_pipeline_create( const struct brw_gs_prog_data *gs_prog_data = &pipeline->gs_prog_data; if (pipeline->gs_vec4 == NO_KERNEL || (extra && extra->disable_vs)) { - anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_GS, .GSEnable = false); + anv_batch_emit(&pipeline->batch, GENX(3DSTATE_GS), .GSEnable = false); } else { urb_offset = 1; urb_length = (gs_prog_data->base.vue_map.num_slots + 1) / 2 - urb_offset; - anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_GS, + anv_batch_emit(&pipeline->batch, GENX(3DSTATE_GS), .KernelStartPointer = pipeline->gs_vec4, .ScratchSpaceBasePointer = pipeline->scratch_start[VK_SHADER_STAGE_GEOMETRY], .PerThreadScratchSpace = scratch_space(&gs_prog_data->base.base), @@ -487,11 +502,15 @@ gen7_graphics_pipeline_create( /* This in the next dword on HSW. */ .ControlDataFormat = gs_prog_data->control_data_format, .ControlDataHeaderSize = gs_prog_data->control_data_header_size_hwords, - .InstanceControl = gs_prog_data->invocations - 1, + .InstanceControl = MAX2(gs_prog_data->invocations, 1) - 1, .DispatchMode = gs_prog_data->base.dispatch_mode, .GSStatisticsEnable = true, .IncludePrimitiveID = gs_prog_data->include_primitive_id, +# if (ANV_IS_HASWELL) + .ReorderMode = REORDER_TRAILING, +# else .ReorderEnable = true, +# endif .GSEnable = true); } @@ -509,7 +528,7 @@ gen7_graphics_pipeline_create( .VertexURBEntryReadOffset = urb_offset, .PointSpriteTextureCoordinateOrigin = UPPERLEFT); - anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_PS, + anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS), .KernelStartPointer0 = pipeline->ps_ksp0, .ScratchSpaceBasePointer = pipeline->scratch_start[VK_SHADER_STAGE_FRAGMENT], .PerThreadScratchSpace = scratch_space(&wm_prog_data->base), @@ -547,9 +566,9 @@ gen7_graphics_pipeline_create( anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_WM, .StatisticsEnable = true, .ThreadDispatchEnable = true, - .LineEndCapAntialiasingRegionWidth = _05pixels, - .LineAntialiasingRegionWidth = _10pixels, - .EarlyDepthStencilControl = NORMAL, + .LineEndCapAntialiasingRegionWidth = 0, /* 0.5 pixels */ + .LineAntialiasingRegionWidth = 1, /* 1.0 pixels */ + .EarlyDepthStencilControl = EDSC_NORMAL, .PointRasterizationRule = RASTRULE_UPPER_RIGHT, .PixelShaderComputedDepthMode = wm_prog_data->computed_depth_mode, .BarycentricInterpolationMode = wm_prog_data->barycentric_interp_modes); @@ -559,37 +578,12 @@ gen7_graphics_pipeline_create( return VK_SUCCESS; } -VkResult gen7_CreateGraphicsPipelines( - VkDevice _device, - VkPipelineCache pipelineCache, - uint32_t count, - const VkGraphicsPipelineCreateInfo* pCreateInfos, - VkPipeline* pPipelines) -{ - VkResult result = VK_SUCCESS; - - unsigned i = 0; - for (; i < count; i++) { - result = gen7_graphics_pipeline_create(_device, &pCreateInfos[i], - NULL, &pPipelines[i]); - if (result != VK_SUCCESS) { - for (unsigned j = 0; j < i; j++) { - anv_DestroyPipeline(_device, pPipelines[j]); - } - - return result; - } - } - - return VK_SUCCESS; -} - -VkResult gen7_compute_pipeline_create( +GENX_FUNC(GEN7, GEN75) VkResult +genX(compute_pipeline_create)( VkDevice _device, const VkComputePipelineCreateInfo* pCreateInfo, VkPipeline* pPipeline) { anv_finishme("primitive_id needs sbe swizzling setup"); - - return vk_error(VK_ERROR_UNAVAILABLE); + abort(); }