X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=targets%2Fsimple.py;h=3d2568483ac7f9b719ca33dc6cdcf05268ca8ac2;hb=097248bce933c06305df672bb94bde7721f08dce;hp=5a18b654433c94d26beab862e35219a671578b50;hpb=1b72b81f9caa9c537cc793b4024f166db3efc5a5;p=litex.git

diff --git a/targets/simple.py b/targets/simple.py
index 5a18b654..3d256848 100644
--- a/targets/simple.py
+++ b/targets/simple.py
@@ -1,63 +1,48 @@
 from migen.fhdl.std import *
 from migen.bus import wishbone
-from migen.genlib.io import DifferentialInput
+from migen.genlib.io import CRG
 
 from misoclib.soc import SoC, mem_decoder
 from misoclib.com.liteeth.phy import LiteEthPHY
-from misoclib.com.liteeth.mac import LiteEthMAC
-
-class _CRG(Module):
-	def __init__(self, clk_crg):
-		self.clock_domains.cd_sys = ClockDomain()
-		self.clock_domains.cd_por = ClockDomain(reset_less=True)
-
-		# Power on Reset (vendor agnostic)
-		rst_n = Signal()
-		self.sync.por += rst_n.eq(1)
-		self.comb += [
-			self.cd_sys.clk.eq(clk_crg),
-			self.cd_por.clk.eq(clk_crg),
-			self.cd_sys.rst.eq(~rst_n)
-		]
+from misoclib.com.liteeth.core.mac import LiteEthMAC
+
 
 class BaseSoC(SoC):
-	def __init__(self, platform, **kwargs):
-		SoC.__init__(self, platform,
-			clk_freq=int((1/(platform.default_clk_period))*1000000000),
-			with_rom=True,
-			with_sdram=True, sdram_size=16*1024,
-			**kwargs)
-		clk_in = platform.request(platform.default_clk_name)
-		clk_crg = Signal()
-		if hasattr(clk_in, "p"):
-			self.specials += DifferentialInput(clk_in.p, clk_in.n, clk_crg)
-		else:
-			self.comb += clk_crg.eq(clk_in)
-		self.submodules.crg = _CRG(clk_crg)
+    def __init__(self, platform, **kwargs):
+        SoC.__init__(self, platform,
+            clk_freq=int((1/(platform.default_clk_period))*1000000000),
+            integrated_rom_size=0x8000,
+            integrated_main_ram_size=16*1024,
+            **kwargs)
+        self.submodules.crg = CRG(platform.request(platform.default_clk_name))
+
 
 class MiniSoC(BaseSoC):
-	csr_map = {
-		"ethphy":		20,
-		"ethmac":		21
-	}
-	csr_map.update(BaseSoC.csr_map)
-
-	interrupt_map = {
-		"ethmac":		2,
-	}
-	interrupt_map.update(BaseSoC.interrupt_map)
-
-	mem_map = {
-		"ethmac":	0x30000000, # (shadow @0xb0000000)
-	}
-	mem_map.update(BaseSoC.mem_map)
-
-	def __init__(self, platform, **kwargs):
-		BaseSoC.__init__(self, platform, **kwargs)
-
-		self.submodules.ethphy = LiteEthPHY(platform.request("eth_clocks"), platform.request("eth"))
-		self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", with_hw_preamble_crc=False)
-		self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
-		self.add_memory_region("ethmac", self.mem_map["ethmac"]+0x80000000, 0x2000)
+    csr_map = {
+        "ethphy": 20,
+        "ethmac": 21
+    }
+    csr_map.update(BaseSoC.csr_map)
+
+    interrupt_map = {
+        "ethmac": 2,
+    }
+    interrupt_map.update(BaseSoC.interrupt_map)
+
+    mem_map = {
+        "ethmac": 0x30000000,  # (shadow @0xb0000000)
+    }
+    mem_map.update(BaseSoC.mem_map)
+
+    def __init__(self, platform, **kwargs):
+        BaseSoC.__init__(self, platform, **kwargs)
+
+        self.submodules.ethphy = LiteEthPHY(platform.request("eth_clocks"),
+                                            platform.request("eth"))
+        self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
+                                            interface="wishbone",
+                                            with_preamble_crc=False)
+        self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
+        self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
 
 default_subtarget = BaseSoC