X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=techlibs%2Fefinix%2Fcells_sim.v;h=22c7bc776dafa88d36d2d2801ae9dffbbb5edeee;hb=6b0ac04698d62c33bcf9309d9f69d09b7b614c1e;hp=2fc2034a6508a5bb411285808266274484ba20c0;hpb=d99b1e32618f8aa92c01eb0ac5d08486f411cca0;p=yosys.git

diff --git a/techlibs/efinix/cells_sim.v b/techlibs/efinix/cells_sim.v
index 2fc2034a6..22c7bc776 100644
--- a/techlibs/efinix/cells_sim.v
+++ b/techlibs/efinix/cells_sim.v
@@ -36,6 +36,7 @@ module EFX_FF(
    output reg Q,
    input D,
    input CE,
+   (* clkbuf_sink *)
    input CLK,
    input SR
 );
@@ -59,7 +60,9 @@ module EFX_FF(
    assign ce = CE_POLARITY ? CE : ~CE;
    assign sr = SR_POLARITY ? SR : ~SR;
    assign d = D_POLARITY ? D : ~D;
-  
+
+	initial Q = 1'b0;
+
    generate
    	if (SR_SYNC == 1) 
       begin
@@ -98,6 +101,7 @@ endmodule
 module EFX_GBUFCE(
    input CE,
    input I,
+   (* clkbuf_driver *)
    output O
 );
    parameter CE_POLARITY = 1'b1;
@@ -113,11 +117,13 @@ module EFX_RAM_5K(
    input [WRITE_WIDTH-1:0] WDATA,
    input [WRITE_ADDR_WIDTH-1:0] WADDR,
    input WE, 
+   (* clkbuf_sink *)
    input WCLK,
    input WCLKE, 
    output [READ_WIDTH-1:0] RDATA, 
    input [READ_ADDR_WIDTH-1:0] RADDR,
    input RE, 
+   (* clkbuf_sink *)
    input RCLK
 );
    parameter READ_WIDTH = 20;
@@ -170,4 +176,4 @@ module EFX_RAM_5K(
 			    (WRITE_WIDTH == 10) ? 9 :  // 512x10
 			    (WRITE_WIDTH == 5)  ? 10 : -1; // 1024x5
    
-endmodule
\ No newline at end of file
+endmodule