X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=techlibs%2Fgowin%2Fcells_map.v;h=90eb9b5a435dcc8957fbaa5058f132bffce4e55a;hb=6de500ec08fefe8626033c996fa5c4c1deb7e210;hp=851ef20b262f85ddf19a8252a14b0c9b2e63b115;hpb=802671b22edbedda593d4c256423975786c581a3;p=yosys.git

diff --git a/techlibs/gowin/cells_map.v b/techlibs/gowin/cells_map.v
index 851ef20b2..90eb9b5a4 100644
--- a/techlibs/gowin/cells_map.v
+++ b/techlibs/gowin/cells_map.v
@@ -122,6 +122,13 @@ module	\$_DFFE_NP0P_ (input D, C, R, E, output Q);
 	wire _TECHMAP_REMOVEINIT_Q_ = 1;
 endmodule
 
+module \$__GW_IOBUF (input I, OE, output O, inout IO);
+	IOBUF _TECHMAP_REPLACE_ (.I(I), .O(O), .OEN(~OE), .IO(IO));
+endmodule
+
+module \$__GW_TBUF (input I, OE, output O);
+	TBUF _TECHMAP_REPLACE_ (.I(I), .OEN(~OE), .O(O));
+endmodule
 
 module \$lut (A, Y);
 	parameter WIDTH = 0;