X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=techlibs%2Fgreenpak4%2Fsynth_greenpak4.cc;h=bfbb56d15d129f2a4aec0ebd4eacc778ff118ba3;hb=ff785cdb46d6b1ddc19d5acc21b4d1236b3adf3f;hp=56ea8003e32047ffb3c804c5f13c6100f660f964;hpb=3fc1b9f3fdd7f5e8aca25b266cbfea90b519cc42;p=yosys.git

diff --git a/techlibs/greenpak4/synth_greenpak4.cc b/techlibs/greenpak4/synth_greenpak4.cc
index 56ea8003e..bfbb56d15 100644
--- a/techlibs/greenpak4/synth_greenpak4.cc
+++ b/techlibs/greenpak4/synth_greenpak4.cc
@@ -29,7 +29,7 @@ struct SynthGreenPAK4Pass : public ScriptPass
 {
 	SynthGreenPAK4Pass() : ScriptPass("synth_greenpak4", "synthesis for GreenPAK4 FPGAs") { }
 
-	virtual void help() YS_OVERRIDE
+	void help() YS_OVERRIDE
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -59,7 +59,7 @@ struct SynthGreenPAK4Pass : public ScriptPass
 		log("        do not flatten design before synthesis\n");
 		log("\n");
 		log("    -retime\n");
-		log("        run 'abc' with -dff option\n");
+		log("        run 'abc' with '-dff -D 1' options\n");
 		log("\n");
 		log("\n");
 		log("The following commands are executed by this synthesis command:\n");
@@ -70,7 +70,7 @@ struct SynthGreenPAK4Pass : public ScriptPass
 	string top_opt, part, json_file;
 	bool flatten, retime;
 
-	virtual void clear_flags() YS_OVERRIDE
+	void clear_flags() YS_OVERRIDE
 	{
 		top_opt = "-auto-top";
 		part = "SLG46621V";
@@ -79,7 +79,7 @@ struct SynthGreenPAK4Pass : public ScriptPass
 		retime = false;
 	}
 
-	virtual void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
 		string run_from, run_to;
 		clear_flags();
@@ -120,7 +120,7 @@ struct SynthGreenPAK4Pass : public ScriptPass
 		extra_args(args, argidx, design);
 
 		if (!design->full_selection())
-			log_cmd_error("This comannd only operates on fully selected designs!\n");
+			log_cmd_error("This command only operates on fully selected designs!\n");
 
 		if (part != "SLG46140V" && part != "SLG46620V" && part != "SLG46621V")
 			log_cmd_error("Invalid part name: '%s'\n", part.c_str());
@@ -133,7 +133,7 @@ struct SynthGreenPAK4Pass : public ScriptPass
 		log_pop();
 	}
 
-	virtual void script() YS_OVERRIDE
+	void script() YS_OVERRIDE
 	{
 		if (check_label("begin"))
 		{
@@ -155,17 +155,16 @@ struct SynthGreenPAK4Pass : public ScriptPass
 
 		if (check_label("fine"))
 		{
-			run("extract_counter -pout \\GP_DCMP,\\GP_DAC -maxwidth 14");
+			run("extract_counter -pout GP_DCMP,GP_DAC -maxwidth 14");
 			run("clean");
 			run("opt -fast -mux_undef -undriven -fine");
 			run("memory_map");
 			run("opt -undriven -fine");
-			run("techmap");
-			run("techmap -map +/greenpak4/cells_latch.v");
+			run("techmap -map +/techmap.v -map +/greenpak4/cells_latch.v");
 			run("dfflibmap -prepare -liberty +/greenpak4/gp_dff.lib");
 			run("opt -fast");
 			if (retime || help_mode)
-				run("abc -dff", "(only if -retime)");
+				run("abc -dff -D 1", "(only if -retime)");
 		}
 
 		if (check_label("map_luts"))