X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=techlibs%2Fice40%2Fice40_braminit.cc;h=955860740273560435d440cf5c0bea1632b045ea;hb=ebe396a2ab0269e3c89dfb8161b934228b6a2451;hp=936c189ea2b191561199aa76112d393b2101a4d3;hpb=93ef516d919b40ace2099bc7586bfda8648f0757;p=yosys.git

diff --git a/techlibs/ice40/ice40_braminit.cc b/techlibs/ice40/ice40_braminit.cc
index 936c189ea..955860740 100644
--- a/techlibs/ice40/ice40_braminit.cc
+++ b/techlibs/ice40/ice40_braminit.cc
@@ -1,7 +1,7 @@
 /*
  *  yosys -- Yosys Open SYnthesis Suite
  *
- *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>
  *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
@@ -128,7 +128,7 @@ static void run_ice40_braminit(Module *module)
 
 struct Ice40BRAMInitPass : public Pass {
 	Ice40BRAMInitPass() : Pass("ice40_braminit", "iCE40: perform SB_RAM40_4K initialization from file") { }
-	void help() YS_OVERRIDE
+	void help() override
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
@@ -138,7 +138,7 @@ struct Ice40BRAMInitPass : public Pass {
 		log("parameter and converts it into the required INIT_x attributes\n");
 		log("\n");
 	}
-	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
+	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
 		log_header(design, "Executing ICE40_BRAMINIT pass.\n");