X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=tests%2Fconfigs%2Fo3-timing-mp-ruby.py;h=fb2d56fd1f5e789fc82327269cd8805c00eb89a2;hb=b5a54eb64ebce9c217c1d44cc93aebb7cb508c6d;hp=9bdef5eef2e30be054e54a4736bdedc4e852750e;hpb=b00fe08cc9338cb96a151a8cd3c3d1498c716989;p=gem5.git

diff --git a/tests/configs/o3-timing-mp-ruby.py b/tests/configs/o3-timing-mp-ruby.py
index 9bdef5eef..fb2d56fd1 100644
--- a/tests/configs/o3-timing-mp-ruby.py
+++ b/tests/configs/o3-timing-mp-ruby.py
@@ -38,13 +38,20 @@ import ruby_config
 ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", nb_cores)
 
 # system simulated
-system = System(cpu = cpus, physmem = ruby_memory, membus = CoherentBus())
+system = System(cpu = cpus, physmem = ruby_memory, membus = SystemXBar(),
+                mem_mode = "timing",
+                clk_domain = SrcClockDomain(clock = '1GHz'))
+
+# Create a seperate clock domain for components that should run at
+# CPUs frequency
+system.cpu_clk_domain = SrcClockDomain(clock = '2GHz')
 
 for cpu in cpus:
     # create the interrupt controller
     cpu.createInterruptController()
     cpu.connectAllPorts(system.membus)
-    cpu.clock = '2GHz'
+    # All cpus are associated with cpu_clk_domain
+    cpu.clk_domain = system.cpu_clk_domain
 
 # connect memory to membus
 system.physmem.port = system.membus.master