X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=tests%2Fconfigs%2Fo3-timing.py;h=7aa4793ac6fc7c2a701e7da7385d54a09f81bbf5;hb=893533a1264bb369b47f74493adf30ce22829f34;hp=0dd7be5066721a2bf5f7004a7c9f7fd037f5f163;hpb=866cfaf9dc596d8547e14bc2133fb962776572a7;p=gem5.git

diff --git a/tests/configs/o3-timing.py b/tests/configs/o3-timing.py
index 0dd7be506..7aa4793ac 100644
--- a/tests/configs/o3-timing.py
+++ b/tests/configs/o3-timing.py
@@ -1,4 +1,16 @@
-# Copyright (c) 2006 The Regents of The University of Michigan
+# Copyright (c) 2013 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
 # All rights reserved.
 #
 # Redistribution and use in source and binary forms, with or without
@@ -24,28 +36,20 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #
-# Authors: Steve Reinhardt
+# Authors: Andreas Hansson
 
-import m5
 from m5.objects import *
-m5.AddToPath('../configs/common')
-
-class MyCache(BaseCache):
-    assoc = 2
-    block_size = 64
-    latency = 1
-    mshrs = 10
-    tgts_per_mshr = 5
-
-cpu = DerivO3CPU()
-cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'),
-                              MyCache(size = '2MB'))
-cpu.mem = cpu.dcache
-
-system = System(cpu = cpu,
-                physmem = PhysicalMemory(),
-                membus = Bus())
-system.physmem.port = system.membus.port
-cpu.connectMemPorts(system.membus)
+from m5.defines import buildEnv
+from base_config import *
+from arm_generic import *
+from O3_ARM_v7a import O3_ARM_v7a_3
 
-root = Root(system = system)
+# If we are running ARM regressions, use a more sensible CPU
+# configuration. This makes the results more meaningful, and also
+# increases the coverage of the regressions.
+if buildEnv['TARGET_ISA'] == "arm":
+    root = ArmSESystemUniprocessor(mem_mode='timing', mem_class=DDR3_1600_x64,
+                                   cpu_class=O3_ARM_v7a_3).create_root()
+else:
+    root = BaseSESystemUniprocessor(mem_mode='timing', mem_class=DDR3_1600_x64,
+                                   cpu_class=DerivO3CPU).create_root()