X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=tests%2Fconfigs%2Fsimple-timing.py;h=4b11a5d3ce8b5b972f64a98016227dbe6e466eb6;hb=17dbb49294e06ce3c486648da899973100c633f1;hp=6c4b8232f2db49fa966c32787a4a594ae199fa39;hpb=d32c08c4cc0026e18bdcaf030f6afeec90386fe7;p=gem5.git

diff --git a/tests/configs/simple-timing.py b/tests/configs/simple-timing.py
index 6c4b8232f..4b11a5d3c 100644
--- a/tests/configs/simple-timing.py
+++ b/tests/configs/simple-timing.py
@@ -1,3 +1,15 @@
+# Copyright (c) 2013 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
 # Copyright (c) 2006-2007 The Regents of The University of Michigan
 # All rights reserved.
 #
@@ -24,26 +36,10 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #
-# Authors: Steve Reinhardt
+# Authors: Andreas Hansson
 
-import m5
 from m5.objects import *
+from base_config import *
 
-class MyCache(BaseCache):
-    assoc = 2
-    block_size = 64
-    latency = 1
-    mshrs = 10
-    tgts_per_mshr = 5
-
-cpu = TimingSimpleCPU(cpu_id=0)
-cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'),
-                              MyCache(size = '2MB'))
-system = System(cpu = cpu,
-                physmem = PhysicalMemory(),
-                membus = Bus())
-system.physmem.port = system.membus.port
-cpu.connectMemPorts(system.membus)
-cpu.clock = '2GHz'
-
-root = Root(system = system)
+root = BaseSESystemUniprocessor(mem_mode='timing',
+                                cpu_class=TimingSimpleCPU).create_root()