X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=tests%2Fconfigs%2Fsimple-timing.py;h=bc9d016c5b07e917badd2fe2ea9c47b8182c25e9;hb=06c39a154c4dc8fedcf9fbf77bbcf26f176c469c;hp=6c4b8232f2db49fa966c32787a4a594ae199fa39;hpb=cca881a5316d686f0be6b437e756a9faba43aa02;p=gem5.git

diff --git a/tests/configs/simple-timing.py b/tests/configs/simple-timing.py
index 6c4b8232f..bc9d016c5 100644
--- a/tests/configs/simple-timing.py
+++ b/tests/configs/simple-timing.py
@@ -32,18 +32,22 @@ from m5.objects import *
 class MyCache(BaseCache):
     assoc = 2
     block_size = 64
-    latency = 1
+    latency = '1ns'
     mshrs = 10
     tgts_per_mshr = 5
 
+class MyL1Cache(MyCache):
+    is_top_level = True
+
 cpu = TimingSimpleCPU(cpu_id=0)
-cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'),
-                              MyCache(size = '2MB'))
+cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'),
+                              MyL1Cache(size = '256kB'),
+                              MyCache(size = '2MB', latency='10ns'))
 system = System(cpu = cpu,
                 physmem = PhysicalMemory(),
                 membus = Bus())
 system.physmem.port = system.membus.port
-cpu.connectMemPorts(system.membus)
+cpu.connectAllPorts(system.membus)
 cpu.clock = '2GHz'
 
 root = Root(system = system)