X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=veera.mdwn;h=1c3bd588df40bf6e5f79bbffc8001d3e401478e2;hb=d1c4c5d08320411b1c613e3160d4bcb4906d6224;hp=cbb3a0587d0c9fe9511ddd1158582ef7e68e213e;hpb=1189696b2915bba432175aae9949a174960da4cc;p=libreriscv.git

diff --git a/veera.mdwn b/veera.mdwn
index cbb3a0587..1c3bd588d 100644
--- a/veera.mdwn
+++ b/veera.mdwn
@@ -8,41 +8,24 @@ Helping Core Hardware developers.
 
 ## Currently working on
 
-### NLNet.2019.10.032.Formal
-
-* [Bug #883](https://bugs.libre-soc.org/show_bug.cgi?id=883):
-  add cvc5 and bitwuzla to hdl-yosys-tools
-
 ## Currently deffered
 
  - <https://bugs.libre-soc.org/show_bug.cgi?id=602> Low performance bare minimum functionality SIMD emulator required
 
 ## Completed but not yet submitted:
 
-### NLNet.2019.10.046.Standards
-
-* [Bug #839](https://bugs.libre-soc.org/show_bug.cgi?id=839):
-  SVP64 / Extra-V / ZOLC whitepaper
-
-### NLNet.2019.10.032.Formal
-
-* [Bug #847](https://bugs.libre-soc.org/show_bug.cgi?id=847):
-  dev\-env\-setup script for binutils-gdb for target powerpc64le\-linux\-gnu
-
-### NLNet.2019.10.043.Wishbone
-
-* [Bug #878](https://bugs.libre-soc.org/show_bug.cgi?id=878):
-  image conversion explaining multi-issue
-
 ## Submitted for NLNet RFP
 
 submitted but not confirmed paid:
 
+ - <https://bugs.libre-soc.org/show_bug.cgi?id=907> structure packing SVG
+   - (EUR 400)
+
 ## Paid
 
 donation from NLNet confirmed received:
 
-### NLNet.2019.10.Wishbone
+### NLNet.2019.10.043.Wishbone
 
  - <https://bugs.libre-soc.org/show_bug.cgi?id=595> Convert bitmap images to svg
    - (total EUR 200)
@@ -63,12 +46,20 @@ donation from NLNet confirmed received:
   dev\-env\-setup script for symbiflow \(arty A7\-100T\)
     * &euro;600 out of total of &euro;750
 
-### NLNet.2019.10.Standards
+* [Bug #878](https://bugs.libre-soc.org/show_bug.cgi?id=878):
+  image conversion explaining multi-issue
+    * &euro;400 which is the total amount
+
+### NLNet.2019.10.046.Standards
 
 * [Bug #730](https://bugs.libre-soc.org/show_bug.cgi?id=730):
   adapt ALU test cases to include expected results
     * &euro;700 out of total of &euro;1000
 
+* [Bug #839](https://bugs.libre-soc.org/show_bug.cgi?id=839):
+  SVP64 / Extra-V / ZOLC whitepaper
+    * &euro;700 out of total of &euro;2000
+
 ### NLNet.2019.02
 
 * [Bug #750](https://bugs.libre-soc.org/show_bug.cgi?id=750):
@@ -87,6 +78,16 @@ donation from NLNet confirmed received:
   Document steps for ls2 microwatt hello world for fpga boards
     * &euro;450 out of total of &euro;600
 
+### NLNet.2019.10.032.Formal
+
+* [Bug #847](https://bugs.libre-soc.org/show_bug.cgi?id=847):
+  dev\-env\-setup script for binutils-gdb for target powerpc64le\-linux\-gnu
+    * &euro;450 out of total of &euro;650
+
+* [Bug #883](https://bugs.libre-soc.org/show_bug.cgi?id=883):
+  add cvc5 and bitwuzla to hdl-yosys-tools
+    * &euro;800 which is the total amount
+
 ## Completed
 
  - <http://bugs.libre-riscv.org/show_bug.cgi?id=181> test and install public-inbox