X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=why_a_libresoc.mdwn;h=88e84944218ce98a70e1211611a31c32c7d0bf11;hb=338ea8b7aed7a081bb35153abb31c525af0592a8;hp=73c789ef87efb3e2cd2890f38da8a480f9eee62d;hpb=add43559fe78cce651a00443241a900460cea1d0;p=libreriscv.git diff --git a/why_a_libresoc.mdwn b/why_a_libresoc.mdwn index 73c789ef8..88e849442 100644 --- a/why_a_libresoc.mdwn +++ b/why_a_libresoc.mdwn @@ -1,19 +1,38 @@ -## Why a Libre SOC? +# Why a Libre-SOC? -Its quite hard to guarantee that a performant processors (think pipelined, out-of-order) are functionally perfectly correct. In fact, it often turns out that they [aren’t](https://meltdownattack.com). +## TLDR + +We believe a computer should be safe to use, and this starts with a open processor. + +We also believe that an open processor doesn't mean a weak processor. + +Check out our [mission](../The_Mission). + +## The Lengthier Explanation... + +Its quite hard to guarantee that performant processors (think pipelined, out-of-order) are functionally perfectly correct. In fact, it often turns out that they [aren’t](https://meltdownattack.com). There are entire [dissertations](http://www.kroening.com/diss/diss-kroe.pdf) dedicated to the subject matter of merely functionally verifying a pipeline (this doesn’t even consider out of order execution). -Given the fact that performant bug-free processors no longer exist, how can you trust your processor? The next best thing is to have access to a processor’s design files. Not only have access to them, you must have the freedom to study and improve them. +Given the fact that performant bug-free processors no longer exist [1][2], how can you trust your processor [3]? The next best thing is to have access to a processor’s design files. Not only have access to them, you must have the freedom to study, improve them, run the test suites and be able to improve those too. + +Not only that, you and everyone who has a stake in the success needs to be entirely free from NDAs and other restrictions which prevent and prohibit communication. An example: although you yourself might not have the technical capability to review our SoC, you can always find a third party to pay those who can. However if the source code was under NDA, do you think that would be practical to consider? + +*Collaboration, not competition*. + +Such a processor is referred to as a Libre processor. However, processors themselves are only a part of the picture. Nowadays, most contemporary computing tasks involve artificial intelligence, media consumption, wireless connectivity, etc... Thus, we must deliver an entire Libre-SOC. + +* [1]: +* [2]: +* [3]: -Such a processor is referred to as a Libre processor. However, processors themselves are only a part of the picture. Nowadays, most contemporary computing tasks involve artificial intelligence, media consumption, wireless connectivity, etc... Thus, we must deliver an entire LibreSOC. +# Benefits: Privacy, Safety-Critical, Peace of Mind... -## Benefits: Privacy, Safety-Critical, Peace of Mind... -Our LibreSOC will not have backdoors that plague modern [processors](https://www.csoonline.com/article/3220476/researchers-say-now-you-too-can-disable-intel-me-backdoor-thanks-to-the-nsa.html). +Our Libre-SOC will not have backdoors that plague modern [processors](https://www.csoonline.com/article/3220476/researchers-say-now-you-too-can-disable-intel-me-backdoor-thanks-to-the-nsa.html). There is a very real need for reliable safety critical processors (think airplane, smart car, nuclear power plant, pacemaker...). -LibreSOC posits that it is impossible to trust a processor in a safety critical environment without both access -to that processor's source and a cycle accurate HDL simulator that guarantees developers their code behaves as they -expect. An ISA level simulator is no longer satisfactory. +Libre-SOC posits that it is impossible to trust a processor in a safety critical environment without both access +to that processor's source, a cycle accurate HDL simulator that guarantees developers their code behaves as they +expect, and formal correctness proofs. An ISA level simulator is no longer satisfactory. Refer to this [IEEE article](https://ieeexplore.ieee.org/document/4519604) by Cyberphysical System expert Ed-Lee for more details.