git.libre-soc.org Git - yosys.git/commit - frontends/verific/verific.h

author	Clifford Wolf <clifford@clifford.at>
	Tue, 18 Dec 2018 15:01:22 +0000 (16:01 +0100)
committer	Clifford Wolf <clifford@clifford.at>
	Tue, 18 Dec 2018 15:01:22 +0000 (16:01 +0100)
commit	3d671630e2bf78cd53ef1b678a1bbb63338cbcd2
tree	8345c80d08d31c0f21b5b608340980b3c8af4189	tree
parent	847fd360773d72933f1c728dba0755e0033350a6	commit \| diff

Improve src tagging (using names and attrs) of cells and wires in verific front-end

Signed-off-by: Clifford Wolf <clifford@clifford.at>

frontends/verific/verific.cc		diff \| blob \| history
frontends/verific/verific.h		diff \| blob \| history