git.libre-soc.org Git - microwatt.git/commit - litedram/gen-src/generate.py

author	Benjamin Herrenschmidt <benh@kernel.crashing.org>
	Tue, 12 May 2020 10:27:15 +0000 (20:27 +1000)
committer	Benjamin Herrenschmidt <benh@kernel.crashing.org>
	Sat, 16 May 2020 02:42:58 +0000 (12:42 +1000)
commit	c19b5b8cc7470c68243ceed6339f831747c0be40
tree	2fa3e3aa31a7e94ca0da1b8cb611be043c2bc911	tree
parent	13e84b0bbb7a0ce2bd935bf3c36e601f85c6f8b0	commit \| diff

litedram: Update to new LiteX/LiteDRAM version

Things have changed a bit in upstream LiteX. LiteDRAM now exposes a
wishbone for the CSRs for example.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

20 files changed:

fpga/top-arty.vhdl		diff \| blob \| history
fpga/top-nexys-video.vhdl		diff \| blob \| history
include/console.h		diff \| blob \| history
include/microwatt_soc.h		diff \| blob \| history
lib/console.c		diff \| blob \| history
litedram/gen-src/arty.yml		diff \| blob \| history
litedram/gen-src/generate.py		diff \| blob \| history
litedram/gen-src/nexys-video.yml		diff \| blob \| history
litedram/gen-src/sdram_init/Makefile		diff \| blob \| history
litedram/gen-src/sdram_init/include/system.h		diff \| blob \| history
litedram/gen-src/sdram_init/main.c		diff \| blob \| history
litedram/gen-src/wrapper-mw-init.vhdl		diff \| blob \| history
litedram/gen-src/wrapper-self-init.vhdl		diff \| blob \| history
litedram/generated/arty/litedram-wrapper.vhdl		diff \| blob \| history
litedram/generated/arty/litedram_core.init		diff \| blob \| history
litedram/generated/arty/litedram_core.v		diff \| blob \| history
litedram/generated/nexys-video/litedram-wrapper.vhdl		diff \| blob \| history
litedram/generated/nexys-video/litedram_core.init		diff \| blob \| history
litedram/generated/nexys-video/litedram_core.v		diff \| blob \| history
soc.vhdl		diff \| blob \| history

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