gallium: Create a new PIPE_CAP_TILE_RASTER_ORDER for vc4.
authorEric Anholt <eric@anholt.net>
Thu, 27 Jul 2017 19:05:56 +0000 (12:05 -0700)
committerEric Anholt <eric@anholt.net>
Tue, 10 Oct 2017 17:45:22 +0000 (10:45 -0700)
commitac0051a5075879970f12f614890c9c6d732663b6
tree39a723409f8052a04dce2a5b1d2c9bfac2ba6be7
parent4aa700e0e09d694ecae60ee04b11ca6e7458afe7
gallium: Create a new PIPE_CAP_TILE_RASTER_ORDER for vc4.

Because vc4 can control the order that tiles are rasterized in, we can use
it to implement overlapping blits using normal drawing and
GL_ARB_texture_barrier, as long as we can tell the kernel what order to
render the tiles in.

This commit introduces the core gallium support, vc4 changes will follow.

v2: Fix on the simulator.
v3: Add the cap (disabled) to other drivers, add rst docs for the cap.
v4: Rebase on PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS
v5: Drop vc4 changes from this commit, for clarity.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> (v3)
18 files changed:
src/gallium/docs/source/screen.rst
src/gallium/drivers/etnaviv/etnaviv_screen.c
src/gallium/drivers/freedreno/freedreno_screen.c
src/gallium/drivers/i915/i915_screen.c
src/gallium/drivers/llvmpipe/lp_screen.c
src/gallium/drivers/nouveau/nv30/nv30_screen.c
src/gallium/drivers/nouveau/nv50/nv50_screen.c
src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
src/gallium/drivers/r300/r300_screen.c
src/gallium/drivers/r600/r600_pipe.c
src/gallium/drivers/radeonsi/si_pipe.c
src/gallium/drivers/softpipe/sp_screen.c
src/gallium/drivers/svga/svga_screen.c
src/gallium/drivers/swr/swr_screen.cpp
src/gallium/drivers/vc4/vc4_screen.c
src/gallium/drivers/virgl/virgl_screen.c
src/gallium/include/pipe/p_defines.h
src/gallium/include/pipe/p_state.h