projects / yosys.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: e8da3ea) | patch
Major redesign of expr width/sign detecion (verilog/ast frontend)
authorClifford Wolf <clifford@clifford.at>
Tue, 9 Jul 2013 12:31:57 +0000 (14:31 +0200)
committerClifford Wolf <clifford@clifford.at>
Tue, 9 Jul 2013 12:31:57 +0000 (14:31 +0200)
commit00a6c1d9a57da0e0b0fef07b2d618847ed93a9fd
tree149e564703234381d2c8f03e6698bede1735fd53tree
parente8da3ea7b647f2c1eeba8a84590df7b05ca4e046commit | diff
Major redesign of expr width/sign detecion (verilog/ast frontend)
frontends/ast/ast.h diff | blob | history
frontends/ast/genrtlil.cc diff | blob | history
frontends/verilog/const2ast.cc diff | blob | history
tests/simple/signedexpr.v [new file with mode: 0644] blob
tests/tools/autotest.sh diff | blob | history